1、XGATE和HCS12XIntroductionThe HCS12X microcontroller family offers many enhancements over the HCS12 family; principal among these is the XGate peripheral processor. HCS12X微控制器系列提供了許多增強HCS12系列的，其中主要是XGATE週邊處理器。The XGATE is a programmable core that operates independently of the main CPU, has access to a
2、ll of the S12X peripherals, and features a RISC instruction set.XGATE是一個可編程的核心，運行獨立於主CPU，具有存取所有S12X週邊設備，採用RISC指令集。This application note describes how to configure and use the XGATE.本應用筆記介紹了如何配置和使用的XGATE。The document begins with a discussion of the issues surrounding data coherency in dual core syste
3、ms and how these can be addressed by software.文件首先的討論的問題在雙核心系統中數據的一致性，以及如何將這些軟體可以解決。It goes on, in the following section, to provide some general information and advice on how to set up and initialize the XGATE module.如此下去，在下面的章節中，如何設置和初始化XGATE模組提供一些一般資料和諮詢意見。Finally, it describes the XGATEs various
4、 power saving modes, and provides acomparison of their capabilities and differences最後，它描述了XGATE的各種省電模式，提供了一個比較，他們的能力和差異。Data CoherencyData coherency is the state whereby a set of data is seen as consistent and complete by any process that wishes to examine it. 數據一致性是一組數據被視為一致且完整的任何過程，想研究一下它的狀態。In pr
5、actice, this means that access to the set is forbidden if the data is currently being changed and so is not internally consistent.在實踐中，這意味著設定的存取是被禁止的，如果數據正在被改變，所以內部沒有一致。Example: One process enters some data into a memory area and increments a variable holding the number of entries, while the other p
6、rocess takes the data out of that memory area and decrements this entry count variable. 例如：一個過程進入到記憶體區和遞增的變數保持的項目數的一些數據，而其它過程中取得數據該記憶體區域和遞減計數變數這個項目。A typical code sequence looks like the following:一個典型的碼序列如下所示：1。讀取變數到內部處理器暫存器2。遞增或遞減變數3。寫變數回記憶體中In a multi-tasking system, an interrupt might cause a ta
7、sk switch immediately after reading the variable. 在一個多任務系統中，可能會導致一個中斷任務切換後，立即讀取的變數。The variable might then be read in the other task, decremented and written back, thereby causing the variable to end up in an inconsistent state. 變數可能被讀取的其他任務，遞減寫回，從而導致變數處於不一致的狀態In single processor systems, such code
8、sequences are typically protected by disabling and enabling the interrupt before and after the critical code sequence.在單處理器系統中，這樣的代碼序列通常是保護通過禁用和使能中斷之前和之後的關鍵碼序列。When dealing with any dual-processor architecture, this method does not work.當處理任何雙處理器架構，這種方法不起作用。Strictly speaking, almost every kind of pe
9、ripheral has this kind of issue. 嚴格地說，幾乎每一種周邊有這種問題。For example, an SCI receiver fills the receive buffer when a new byte is received;at the same time, the CPU might read the receive buffer and get conflicting data. 例如，SCI接收器，當接收到一個新的字節填補接收緩衝區;在同一時間，CPU可能會讀取接收緩衝器，並得到衝突數據。In the case of peripherals, i
10、n most cases special flags indicate whether data is available or can be transmitted.在週邊設備的情況下，在大多數情況下，特殊標誌指示數據是否可用，或者可以被發送。In short, each time two or more processes can access the same resource simultaneously, special care has to be taken.總之，每次兩個或多個進程可以同時存取相同的資源，必須採取特殊照顧。XGATE和HCS12X CPU時間多路復用存取的RAM
11、中的方式。S12X CPU在一個週期(25 ns) 存取RAM，而XGATE可以在12.5 ns內是CPU的兩倍，如果S12X CPU不處理的RAM;或時間中的至少一個，與一個接入專用的S12X CPU和其他XGATE。這很好的功能增強的XGATE的通過，以及在CPU，但也增加了數據一致性問題的複雜性。兩個處理器之間的數據交換，避免數據一致性問題的一個簡單方法是使用一個緩衝區。The two processors must honour an underlying agreement that one side writes to the buffer only if the other si
12、de has flagged the buffer as empty, and the other side reads from the buffer only if it has received the full signal.兩個處理器必須履行相關協議，一方只有當對方有標記的緩衝區為空，是否已接收到完整的信號，另一側從緩衝區讀取寫入到緩衝區。Transmit Buffer典型的應用程序可以使用是LIN transmission 及 SPI masters這個簡單的方式。一個發送緩衝區的流程將是如下：1. CPU fills the buffer.CPU填入緩衝區。2. CPU sign
13、als the XGATE module that the data is ready for transmission.(This can be caused, for instance, by enabling the transmit request inside the peripheral.)CPUXGATE模塊，數據已準備好用於傳輸的信號。（這可能是由於，例如，通過使內部的外圍設備的發送請求）。3. The XGATE module gets a transmit service request.XGATE模塊得到一個發送服務請求。4. The XGATE module sends
14、 out the data to the peripheral.XGATE模塊發送數據的外設。5. Once finished, the XGATE disables transmit request of the peripheral.一旦完成後，XGATE禁止週邊的發送請求。6. The XGATE signals to the CPU (via an interrupt, for example) that the transfer is completed.XGATE的信號到CPU（例如:通過中斷），傳輸完成。7. The CPU can now start again at step
15、 1.現在CPU可以重新開始在第1步發送或接收緩衝區的數據結構Receive BufferThe flow for receiving data from a peripheral device and storing it into a buffer is very similar.周邊裝置及並儲存到緩衝區中和接收數據的流程是非常相似的。However, care must be taken that no new data is received before the buffer is read.但是，必須小心讀緩衝區之前沒有接收到新數據。This is not an issue for
16、 a LIN node, or for SPI protocols, for example, as the sending of data is actually controlled by a transmit process, i.e. controlled by the CPU, itself.這不是LIN節點或SPI協議的問題，例如作為數據發送實際上是由一個發送過程中控制，即由CPU自已本身控制。If the receive process runs asynchronous to the CPU activities, different methods must be used,
17、 as shown below.如果接收過程運行非同步於CPU，可以使用不同的方法如下所示。對於接收處理，用於發送相同的結構都可以使用。1。XGATE服務是從周邊接收服務請求。2。XGATE模組填入緩衝區直到被填滿在預定義bytes或接收一個結束標誌。3。XGATE的傳輸完成時通知給CPU（例如，通過中斷）。4。CPU從緩衝區中提取數據然後可以進行進一步的處理。另一種技術是不使用信號量並可以允許覆蓋的數據。The reading side must set a “” before reading data, and verify that this guard is still set aft
18、er the read sequence is completed.讀方面必須讀取數據之前設置一個“警衛(guard)”，並確認這個守衛讀取序列完成後仍可設置。這種技術的優點相較於一個信號技術（見下文），是讀取數據的過程中從來沒有被停止，甚至不需要阻止中斷。這樣做的缺點是，可能必須重複進行數據的讀出。一個程序開始之前要填補一個緩衝區，而變數Guard要遞增。數據完全寫入到緩衝區中之後，變數Guard再次遞增。Before the read process starts to read the data buffer, it creates a copy of the current guard
19、 (OldG).讀程序開始到讀取數據的緩衝區之前，它會建立一個復制的current guard（OldG）。Assuming the variable Guard has been initialized to $0000, an odd number indicates that a write is just in progress, so the read process keeps polling the variable Guard until it becomes even, at which time it starts to read the data.假設變數guard已初始
20、化到$ 0000，程序在寫以奇數表示，所以讀程序不斷輪詢變數guard，直到它變得偶數，此時它開始讀取數據。At the end of the read process, the variable Guard is compared to the saved one, OldG. 在讀過程結束時，該變數Guard已存取與OldG相比。If they are not equal, then a write has occurred while reading, thereby corrupting the read data. 如果它們不相等，那麼在寫時發生讀，從而破壞讀出的數據。In this
21、 case, the process must be repeated. Figure 2 shows the flow.在這種情況下，該過程必須重複。圖2表示出流程。This technique can be used in XGATE to S12X CPU or S12X to XGATE direction.這種技術可以用在XGATE到S12X CPU或S12X到XGATE的方向。互斥（互斥變量）或信號燈In many cases, concurrent access to the same resource is avoided by using a mutex (mutually
22、exclusive RAM variable) or a semaphore1.在許多情況下，並發行存取相同的資源是為了避免使用互斥（互斥的RAM變量）或semaphore1的。However, for the S12X CPU and the XGATE module it is impossible to use a read-modify-write mutex or semaphore in RAM to indicate exclusive access to any resources, because it takes several cycles to read a RAM v
23、ariable, test its contents, and write the modified variable back to RAM. Between the read and the write, the variable is “in transition” in an internal register of either the CPU or the XGATE module然而，對於S12X CPU和XGATE模組是不可能使用一個讀 - 修改 - 寫在RAM中的互斥或信號量去表示互斥存取的任何資源，因為它需要幾個週期來讀取的RAM變數，測試它的內容，並寫回RAM修改變數。讀
24、與寫之間變數是“轉換”在CPU或XGATE模組的內部暫存器。If, now, the other module accesses the variable while being in transition, a write-back will result in an inconsistent state現在，如果存取其他模組的變數在轉型時，一個寫回將導致不一致的特質狀態。XGATE可以提供專為此目的而設計的一組8個硬件信號燈。這樣的信號量，可以在以下三種狀態之一1。未發布2。指定給S12X CPU過程3。指定給XGATE過程這三種狀態之間的轉換處理過程如下1。設置信號燈。XGATE pro
25、vides a dedicated instruction called SSEM with either a 3-bit immediate value or a register as operand.XGATE提供專用指令稱為SSEM，一個3位立即值或其暫存器作為操作數。The carry flag is set if the XGATE could successfully lock the semaphore, and is cleared if the semaphore is already locked.如果XGATE可以成功鎖定信號，進位標誌被設置，如果信號已被鎖定，進位標誌
26、被被清除。The S12 CPU accesses the semaphore via the XGSEM peripheral register and requires a two step approach to set and check the semaphore, using the C-Macros shown below.S12 CPU存取的信號量通過週邊暫存器XGSEM和需要兩個步驟的方法來設置，並檢查信號量，使用如下所示的C宏2。釋放信號量。XGATE provides a dedicated instruction called CSEM with either a 3-
27、bit immediate value or a register as operand to release the semaphore.XGATE提供了一個專用的指令稱為CSEM，3位立即數或暫存器作為操作數來釋放信號。Again, the S12 CPU accesses the semaphore via the XGSEM peripheral register.同樣，S12的CPU存取通過信號燈的XGSEM周邊寄存器。The hardware assures a clear priority, in case the two “get” commands areissued at
28、the same time.硬體確保明確的優先級，此情況下兩個“get”命令在同一時間發出。The “release” command should be issued only by the process associated with the semaphore應只與信號相關的程序發出“釋放”命令2. Why does this not happen in a normal multitasking operation system using semaphores or alike to guarantee exclusive access of one task to a share
29、d resource? 2。為什麼這不是發生在一個正常的多任務操作系統使用信號燈或類似以確保一項任務獨占存取共享資源？Most CPUs have annoninterruptible “read, test, modify, write” instruction so the variable is never “in transition”. 大多數CPU有一個不可中斷的“讀，測試，修改，寫”的指令，因此變數是從來沒有的“轉型”。The HCS12 must emulate this by using disable and enable interrupts, around the re
30、ad-modify-write sequence, while the HCS12X CPU has a dedicated instruction (BTAS).HCS12必須模擬這種使用禁用和啟用中斷，周圍的讀 - 修改 - 寫序列，HCS12X CPU專用指令（BTAS）。Semaphore StatesFIFOA well known technique for de-coupling two asynchronous data streams is a First-In-First-Out (FIFO) data structure.一位知名去耦兩個非同步數據流技術是一種先入先出（F
31、IFO）的數據結構。 A FIFO is most useful if a stream of data has to be received, where the individual bytes (or whole messages) are received in bursts, too fast for the CPU to handle, even though the overall performance of the CPU is more than sufficient to sustain the average data rate. 如果數據流的形式被接收，FIFO是最有
32、用的，其中的各別bytes（或整個訊息）中接收到脈衝串，速度太快由CPU來處理，即使在CPU的整體性能是綽綽有餘維持的平均數據速率。通過使用一個FIFO，在CPU的等待時間要求，可以顯著減少。A typical example is the 16550 UART found in almost every personal computer, which uses a 16-byte deep FIFO to buffer the incoming and outgoing data.一個典型的例子是16550 UART發現幾乎每一台個人電腦，它使用一個16字節的深FIFO緩衝傳入和傳出的數據。The main issue with any FIFO is that at least one common bit of information is re
