1、显示码由16位组成，对应16根列线的值，列线值（显示码）由两个字节来表示。每个字节8位，代表8列，从第一行开始显示；并关闭其他行；然后第二行显示；并关闭其他行。第三行第十六行 第一行，第二行第十六行如此周而复始,由于扫描频率很快，所以人眼视觉暂留效应，会感觉16行都被显示了，并且显示不同的内容。实际上任何时刻只点亮了一行。2.汉字取模3.取模软件的用法四、 实验结果记录（如输出波形，显示结果等） 五、 主要源代码amodule hanzi1（mainclk,rst,DATA,SRCK,RCK,AB,CLK）;input mainclk,rst;output DATA,SRCK,RCK,AB,C
2、LK;reg10:0 count;wire clk_24;reg3:0 state;0 cnt_164,cnt_595;reg15:0 temp;/reg4:0 cnt_c;reg14:0 delay_164;reg13:0 delay_595;reg SRCK,RCK,AB,CLK,DATA;reg 15:0 table115:0;reg 3:0 sel;reg 26:0 count1;reg 2:0state1;/0x00,0x80,0xF8,0x88,0x08,0x8C,0x08,0x90,0x78,0xA0,0x40,0xC0,0x40,0x80,0x43,0xFE,/0xF8,0xA
3、0,0x48,0xA0,0x08,0x90,0x08,0x90,0x08,0x88,0x08,0xA6,0x29,0xC4,0x10,0x80,/*张,0*/0x7E,0xFC,0x22,0x44,0x12,0x24,0x0A,0x14,0x12,0x24,0x29,0x44,0x0C,0x80,0x1F,0xFC,/0x10,0x80,0x3F,0xFC,0x50,0x80,0x1F,0xFC,0x10,0x80,0x10,0x80,0x1F,0xFE,0x10,0x00,/*翟always （posedge mainclk） count1=count1=49999999 ? 0 :coun
4、t1+1; begin if（count1=49999999） state1=state1=5 ? state1+1; else state1=state1; end/0x01,0x00,0x21,0x10,0x19,0x18,0x0D,0x10,0x09,0x20,0x01,0x04,0x7F,0xFE,0x04,0x40,/0x04,0x40,0x04,0x40,0x04,0x40,0x08,0x42,0x08,0x42,0x10,0x42,0x20,0x3E,0x40,0x00,/*光always （state1） if（state1=0） begin table10=16h0100;
5、table11=16h2110; table12=16h1918; table13=16h0d10; table14=16h0920; table15=16h0104; table16=16h7ffe; table17=16h0440; table18=16 table19=16 table110=16 table111=16h0842; table112=16 table113=16h1042; table114=16h203e; table115=16h4000; end/0x01,0x00,0x01,0x00,0x01,0x00,0x3F,0xF8,0x21,0x08,0x21,0x08
6、,0x3F,0xF8,0x21,0x08,/0x21,0x08,0x21,0x08,0x3F,0xF8,0x21,0x08,0x01,0x02,0x01,0x02,0x00,0xFE,0x00,0x00,/*电 else if（state1=1）h3FF8;h2108;h0102;h00FE;h0000;,2*/ else if（state1=2）h0080;hF888;h088C;h0890;h78A0;h40C0;h4080;h43FE;hF8A0;h48A0;h0888;h08A6;h29C4;h1080;/0x7E,0xFC,0x22,0x44,0x12,0x24,0x0A,0x14,
7、0x12,0x24,0x29,0x44,0x0C,0x80,0x1F,0xFC,3*/ else if（state1=3）h7EFC;h2244;h1224;h0A14;h2944;h0C80;h1FFC;h3FFC;h5080;h1FFE;h1000;/0x01,0x08,0x10,0x8C,0x0C,0xC8,0x08,0x90,0x7F,0xFE,0x40,0x04,0x8F,0xE8,0x00,0x40,/0x00,0x80,0x7F,0xFE,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x02,0x80,0x01,0x00,/*学,4*/ els
8、e if（state1=4）h0108;h108C;h0CC8;h7FFE;h4004;h8FE8;h0040;h0280;/0x00,0x80,0xF8,0x40,0x8F,0xFE,0x94,0x04,0xA0,0x00,0xA3,0xF8,0x90,0x00,0x88,0x00,/0x8F,0xFE,0xA9,0x20,0x91,0x20,0x81,0x20,0x82,0x22,0x82,0x22,0x84,0x22,0x88,0x1E,/*院,5*/ else if（state1=5）hF840;h8FFE;h9404;hA000;hA3F8;h9000;h8800;hA920;h91
9、20;h8120;h8222;h8422;h881E; end endalways（posedge mainclk）count=count+1;assign clk_24=count3;always（posedge clk_24 or negedge rst）if（!rst）beginstate=0;cnt_595=0;cnt_164=0;temp=16endelsecase（state）0: begin AB=0; CLK=0;state=state+1;1: begin CLK=1; state=state+1;2: begin CLK=0; RCK=0;3: begin temp=tab
10、le1cnt_164;4: begin SRCK=0; DATA=tempcnt_595;5: begin SRCK=1;6: if（cnt_595 = 15） begin state=7; else begin state=4; cnt_595=cnt_595+1;7: begin AB=1;8: begin RCK=1;9:10:/*if（delay_1641000） begin delay_164=delay_164+1; begin delay_164=0;end*/ begin state=state+1;11: if（cnt_164 = 15） begin state=0; begin state=2; cnt_164=cnt_164+1;default:begin state=0; endcaseendmodule6、实验遇到的问题及解决办法（余留问题、体会等）代码下载后总是不能正确显示，以为代码有问题，最后更换点阵屏后正确了。顶层实体名称和工程名必须一样；顶层实体为bdf文件。verilog文件（.v）都为子模块，不能与工程名或顶层实体名一样。所有verilog文件（.v）里面的模块名必须和这个verilog文件（.v）的文件名一样.
