1、微波炉控制器软件设计-KZQ.VHDLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;ENTITY KZQ IS PORT(RESET,SET_T,START,TEST,CLK,DONE: IN STD_LOGIC; COOK,LD_8888,LD_CLK,LD_DONE:OUT STD_LOGIC);END ENTITY KZQ;ARCHITECTURE ART OF KZQ IS TYPE STATE_TYPE IS(IDLE,LAMP_TEST,SET_CLOCK,TIMER,DONE_MSG);
2、SIGNAL NXT_STATE,CURR_STATE:STATE_TYPE; BEGIN PROCESS(CLK,RESET) IS BEGIN IF RESET=1 THEN CURR_STATE=IDLE; ELSIF CLKEVENT AND CLK=1 THEN CURR_STATE=NXT_STATE; END IF; END PROCESS; PROCESS(CLK,CURR_STATE,SET_T,START,TEST,DONE) IS BEGIN NXT_STATE=IDLE; -DEFAULT NEXT STATE IS IDLE; LD_8888=0; LD_DONE=0
3、; LD_CLK=0; COOK LD_8888=1; COOK LD_CLK=1; COOK LD_DONE=1; COOK IF(TEST=1) THEN NXT_STATE=LAMP_TEST; LD_8888=1; ELSIF SET_T=1 THEN NXT_STATE=SET_CLOCK; LD_CLK=1; ELSIF (START=1) AND (DONE=0) THEN NXT_STATE=TIMER; COOK IF DONE=1 THEN NXT_STATE=DONE_MSG; LD_DONE=1; ELSE NXT_STATE=TIMER; COOK=1; END IF
4、; END CASE; END PROCESS;END ARCHITECTURE ART;-PWMKZQ.VHDLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY PKZQ IS PORT(CLK,ENA: IN STD_LOGIC; MODE0: IN STD_LOGIC_VECTOR(1 DOWNTO 0); POUT: OUT STD_LOGIC);END ENTITY PKZQ;ARCHITECTURE ART OF PK
5、ZQ ISSIGNAL COUNT : STD_LOGIC_VECTOR ( 2 DOWNTO 0);SIGNAL Z : STD_LOGIC:=0;BEGINPROCESS (CLK,ENA) ISBEGIN IF(ENA=0)THEN COUNT=000; ELSE IF(CLK=1AND CLKEVENT) THEN IF(COUNT=111) THEN COUNT=000; ELSE COUNTZZZZZZZZZZZZ=0; END CASE; END IF; END PROCESS;PROCESS (CLK, Z) ISBEGIN IF ( CLKEVENT AND CLK=1 )
6、THEN POUT=Z; END IF;END PROCESS;END ARCHITECTURE ART;-ZZQ.VHDLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;ENTITY ZZQ IS PORT(DATA1: IN STD_LOGIC_VECTOR(15 DOWNTO 0); LD_8888:IN STD_LOGIC; LD_CLK: IN STD_LOGIC; LD_DONE:IN STD_LOGIC; DATA2:OUT STD_LOGIC_VECTOR(15 DOWNTO 0); LO
7、AD:OUT STD_LOGIC);END ENTITY ZZQ;ARCHITECTURE ART OF ZZQ IS BEGIN PROCESS(DATA1,LD_8888,LD_CLK,LD_DONE) IS CONSTANT ALL_8:STD_LOGIC_VECTOR(15 DOWNTO 0):=1000100010001000; CONSTANT DONE:STD_LOGIC_VECTOR(15 DOWNTO 0):= 1010101111001101; VARIABLE TEMP:STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN LOAD DATA2 DATA
8、2 DATA2 NULL; END CASE; END PROCESS;END ARCHITECTURE ART; -DCNT10.VHDLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY DCNT10 IS PORT(CLK:IN STD_LOGIC; LOAD:IN STD_LOGIC; ENA: IN STD_LOGIC; DATAIN:IN STD_LOGIC_VECTOR(3 DOWNTO 0); CQ:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); CAR
9、RY_OUT: OUT STD_LOGIC );END ENTITY DCNT10; ARCHITECTURE ART OF DCNT10 IS SIGNAL CQI:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN PROCESS(CLK,LOAD,ENA) IS BEGIN IF LOAD=1 THEN CQI=DATAIN; ELSIF CLKEVENT AND CLK=1 THEN IF ENA=1 THEN IF CQI=0000 THEN CQI=1001; ELSE CQI=CQI-1; END IF; END IF; END IF; END PROCESS
10、; PROCESS(CLK,CQI) IS BEGIN IF CLKEVENT AND CLK=1 THEN IF CQI=0000 THEN CARRY_OUT=1;ELSE CARRY_OUT=0;END IF; END IF; END PROCESS; CQ=CQI;END ARCHITECTURE ART;-DCNT6.VHDLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY DCNT6 IS PORT(CLK:IN STD_LOGIC; LOAD:IN STD_LOGIC;
11、ENA: IN STD_LOGIC; DATAIN:IN STD_LOGIC_VECTOR(3 DOWNTO 0); CQ:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); CARRY_OUT: OUT STD_LOGIC );END ENTITY DCNT6; ARCHITECTURE ART OF DCNT6 ISSIGNAL CQI:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN PROCESS(CLK,LOAD,ENA) IS BEGIN IF LOAD=1 THEN CQI=DATAIN; ELSIF CLKEVENT AND CLK=1 T
12、HEN IF ENA=1 THEN IF CQI=0000 THEN CQI=0101; ELSE CQI=CQI-1; END IF; END IF; END IF;END PROCESS; PROCESS(CLK,CQI) IS BEGIN IF CLKEVENT AND CLK=1 THEN IF CQI=0000 THEN CARRY_OUT=1; ELSE CARRY_OUT=0; END IF; END IF; END PROCESS; CQ=CQI;END ARCHITECTURE ART;-JSQ.VHDLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.
13、ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;ENTITY JSQ IS PORT(COOK:IN STD_LOGIC; DATA3: IN STD_LOGIC_VECTOR(15 DOWNTO 0); LOAD:IN STD_LOGIC; CLK: IN STD_LOGIC; SEC_L:OUT STD_LOGIC_VECTOR(3 TO 0); SEC_H:OUT STD_LOGIC_VECTOR(3 TO 0); MIN_L:OUT STD_LOGIC_VECTOR(3 TO 0); MIN_H:OUT
14、STD_LOGIC_VECTOR(3 TO 0); DONE:OUT STD_LOGIC);END ENTITY JSQ;ARCHITECTURE ART OF JSQ IS COMPONENT DCNT10 IS PORT(CLK,LOAD,ENA:IN STD_LOGIC; DATAIN:IN STD_LOGIC_VECTOR(3 DOWNTO 0); CQ:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); CARRY_OUT:OUT STD_LOGIC); END COMPONENT DCNT10; COMPONENT DCNT6 IS PORT(CLK,LOAD,EN
15、A:IN STD_LOGIC; DATAIN:IN STD_LOGIC_VECTOR(3 DOWNTO 0); CQ:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); CARRY_OUT:OUT STD_LOGIC); END COMPONENT DCNT6; SIGNAL NEWCLK:STD_LOGIC; SIGNAL S1:STD_LOGIC; SIGNAL S2:STD_LOGIC; SIGNAL S3:STD_LOGIC; SIGNAL S4:STD_LOGIC; BEGIN U1:DCNT10 PORT MAP(CLK,LOAD,COOK,DATA3(3 DOWN
16、TO 0),SEC_L,S1); U2:DCNT6 PORT MAP(S1,LOAD,COOK,DATA3(7 DOWNTO 4),SEC_H,S2); U3:DCNT10 PORT MAP(S2,LOAD,COOK,DATA3(11 DOWNTO 8),MIN_L,S3); U4:DCNT6 PORT MAP(S3,LOAD,COOK,DATA3(15 DOWNTO 12),MIN_H,S4); DONEDOUT7DOUT7DOUT7DOUT7DOUT7DOUT7DOUT7DOUT7DOUT7DOUT7DOUT7DOUT7DOUT7DOUT7DOUT7=0000000; END CASE;
17、END PROCESS;END ARCHITECTURE ART;-WBLKZQ.VHDLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;ENTITY WBLKZQ IS PORT(RESET1,SET_T1,START1,TEST1,CLKIN:IN STD_LOGIC; MODE:IN STD_LOGIC_VECTOR(1 DOWNTO 0); DATA0:IN STD_LOGIC_VECTOR(15 DOWNTO 0); PWM,COO
18、K1:OUT STD_LOGIC; SEC_L1,SEC_H1,MIN_L1,MIN_H1:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);END ENTITY WBLKZQ;ARCHITECTURE ART OFWBLKZQ IS COMPONENT KZQ IS PORT(RESET,SET_T,START,TEST,CLK,DONE:IN STD_LOGIC; COOK,LD_8888,LD_CLK,LD_DONE:OUT STD_LOGIC); END COMPONENT KZQ; COMPONENT PKZQ IS PORT(ENA,CLK:IN STD_LOGIC
19、 MODE0:IN STD_LOGIC_VECTOR(1 DOWNTO 0); POUT:OUT STD_LOGIC); END COMPONENT PKZQ; COMPONENT ZZQ IS PORT(LD_8888,LD_CLK,LD_DONE:IN STD_LOGIC; DATA1:IN STD_LOGIC_VECTOR(15 DOWNTO 0); LOAD:OUT STD_LOGIC; DATA2:OUT STD_LOGIC_VECTOR(15 DOWN TO 0); END COMPONENT ZZQ; COMPONENT JSQ IS PORT(CLK,COOK,LOAD:IN
20、STD_LOGIC; DATA3:IN STD_LOGIC_VECTOR(15 DOWNTO 0); DONE:OUT STD_LOGIC; SEC_L,SEC_H,MIN_L,MIN_H:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); END COMPONENT JSQ; COMPONENT YMQ47 IS PORT(AIN4:IN STO_LOGIC_VECTOR(3 DOWNTO 0); DOUTT:OUT STD_LOGIC_VECTOR(6 DOWNTO 0); END COMPONENT YMQ47; SIGNAL S2:STD_LOGIC; SIGNAL S
21、3:STD_LOGIC; SIGNAL S4:STD_LOGIC_VECTOR(15 DOWNTO 0); SIGNAL S5:STD_LOGIC; SIGNAL S6:STD_LOGIC; SIGNAL S7:STD_LOGIC; SIGNAL S8:STD_LOGIC; SIGNAL S9:STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL S10:STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL S11:STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL S12:STD_LOGIC_VECTOR(3 DOWNTO 0);
22、 BEGIN U1:KZQ PORT MAP(RESET1,SET_T1,START1,TEST1,CLKIN,S3,S2,S6,S7,S8); U2:PKZQ PORT MAP(S2,CLKIN,MODE0(1 DOWNTO 0),PWM); U3:ZZQ PORT MAP(S6,S7,S8,DATA0(15 DOWNTO 0),S5,S4(15 DOWNTO 0); U4:JSQ PORT MAP(CLKIN,S2,S5,S4(15 DOWNTO 0),S3,S9(3 DOWNTO 0),S10(3 DOWNTO 0),S11(3 DOWNTO 0),S12(3 DOWNTO 0); U5:YMQ47 PORT MAP(S9(3 DOWNTO 0),SEC_L1(6 DOWNTO 0); U6:YMQ47 PORT MAP(S10(3 DOWNTO 0),SEC_H1(6 DOWNTO 0); U7:YMQ47 PORT MAP(S11(3 DOWNTO 0),MIN_L1(6 DOWNTO 0); U8:YMQ47 PORT MAP(S12(3 DOWNTO 0),MIN_H1(6 DOWNTO 0); COOK1=S2; END ARCHITECTUER ART;
