微波炉控制器软件设计.docx
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- 上传时间:2023-06-08
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- 页数:14
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微波炉控制器软件设计.docx
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微波炉控制器软件设计
--KZQ.VHD
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_ARITH.ALL;
ENTITYKZQIS
PORT(RESET,SET_T,START,TEST,CLK,DONE:
INSTD_LOGIC;
COOK,LD_8888,LD_CLK,LD_DONE:
OUTSTD_LOGIC);
ENDENTITYKZQ;
ARCHITECTUREARTOFKZQIS
TYPESTATE_TYPEIS(IDLE,LAMP_TEST,SET_CLOCK,TIMER,DONE_MSG);
SIGNALNXT_STATE,CURR_STATE:
STATE_TYPE;
BEGIN
PROCESS(CLK,RESET)IS
BEGIN
IFRESET='1'THEN
CURR_STATE<=IDLE;
ELSIFCLK'EVENTANDCLK='1'THEN
CURR_STATE<=NXT_STATE;
ENDIF;
ENDPROCESS;
PROCESS(CLK,CURR_STATE,SET_T,START,TEST,DONE)IS
BEGIN
NXT_STATE<=IDLE;--DEFAULTNEXTSTATEISIDLE;
LD_8888<='0';
LD_DONE<='0';
LD_CLK<='0';
COOK<='0';
CASECURR_STATEIS
WHENLAMP_TEST=>LD_8888<='1';COOK<='0';
WHENSET_CLOCK=>LD_CLK<='1';COOK<='0';
WHENDONE_MSG=>LD_DONE<='1';COOK<='0';
WHENIDLE=>
IF(TEST='1')THEN
NXT_STATE<=LAMP_TEST;
LD_8888<='1';
ELSIFSET_T='1'THEN
NXT_STATE<=SET_CLOCK;
LD_CLK<='1';
ELSIF((START='1')AND(DONE='0'))THEN
NXT_STATE<=TIMER;
COOK<='1';
ENDIF;
WHENTIMER=>
IFDONE='1'THEN
NXT_STATE<=DONE_MSG;
LD_DONE<='1';
ELSE
NXT_STATE<=TIMER;
COOK<='1';
ENDIF;
ENDCASE;
ENDPROCESS;
ENDARCHITECTUREART;
--PWMKZQ.VHD
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_ARITH.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYPKZQIS
PORT(CLK,ENA:
INSTD_LOGIC;
MODE0:
INSTD_LOGIC_VECTOR(1DOWNTO0);
POUT:
OUTSTD_LOGIC);
ENDENTITYPKZQ;
ARCHITECTUREARTOFPKZQIS
SIGNALCOUNT:
STD_LOGIC_VECTOR(2DOWNTO0);
SIGNALZ:
STD_LOGIC:
='0';
BEGIN
PROCESS(CLK,ENA)IS
BEGIN
IF(ENA='0')THENCOUNT<="000";
ELSE
IF(CLK='1'ANDCLK'EVENT)THEN
IF(COUNT="111")THENCOUNT<="000";
ELSECOUNT<=COUNT+1;
ENDIF;
ENDIF;
ENDIF;
ENDPROCESS;
PROCESS(COUNT)IS
BEGIN
IF(MODE0="00")THEN
CASECOUNTIS
WHEN"000"=>Z<='1';
WHENOTHERS=>Z<='0';
ENDCASE;
ELSIF(MODE0="01")THEN
CASECOUNTIS
WHEN"000"=>Z<='1';
WHEN"001"=>Z<='1';
WHEN"010"=>Z<='1';
WHENOTHERS=>Z<='0';
ENDCASE;
ELSIF(MODE0="10")THEN
CASECOUNTIS
WHEN"000"=>Z<='1';
WHEN"001"=>Z<='1';
WHEN"010"=>Z<='1';
WHEN"011"=>Z<='1';
WHEN"100"=>Z<='1';
WHENOTHERS=>Z<='0';
ENDCASE;
ENDIF;
ENDPROCESS;
PROCESS(CLK,Z)IS
BEGIN
IF(CLK'EVENTANDCLK='1')THEN
POUT<=Z;
ENDIF;
ENDPROCESS;
ENDARCHITECTUREART;
--ZZQ.VHD
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_ARITH.ALL;
ENTITYZZQIS
PORT(DATA1:
INSTD_LOGIC_VECTOR(15DOWNTO0);
LD_8888:
INSTD_LOGIC;
LD_CLK:
INSTD_LOGIC;
LD_DONE:
INSTD_LOGIC;
DATA2:
OUTSTD_LOGIC_VECTOR(15DOWNTO0);
LOAD:
OUTSTD_LOGIC);
ENDENTITYZZQ;
ARCHITECTUREARTOFZZQIS
BEGIN
PROCESS(DATA1,LD_8888,LD_CLK,LD_DONE)IS
CONSTANTALL_8:
STD_LOGIC_VECTOR(15DOWNTO0):
="1000100010001000";
CONSTANTDONE:
STD_LOGIC_VECTOR(15DOWNTO0):
="1010101111001101";
VARIABLETEMP:
STD_LOGIC_VECTOR(2DOWNTO0);
BEGIN
LOAD<=LD_8888ORLD_DONEORLD_CLK;
TEMP:
=LD_8888&LD_DONE&LD_CLK;
CASETEMPIS
WHEN"100"=>DATA2<=ALL_8;--LOAD_8888=1
WHEN"010"=>DATA2<=DONE;--LOAD_DONE
WHEN"001"=>DATA2<=DATA1;--LOAD_CLK
WHENOTHERS=>NULL;
ENDCASE;
ENDPROCESS;
ENDARCHITECTUREART;
--DCNT10.VHD
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYDCNT10IS
PORT(CLK:
INSTD_LOGIC;
LOAD:
INSTD_LOGIC;
ENA:
INSTD_LOGIC;
DATAIN:
INSTD_LOGIC_VECTOR(3DOWNTO0);
CQ:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
CARRY_OUT:
OUTSTD_LOGIC);
ENDENTITYDCNT10;
ARCHITECTUREARTOFDCNT10IS
SIGNALCQI:
STD_LOGIC_VECTOR(3DOWNTO0);
BEGIN
PROCESS(CLK,LOAD,ENA)IS
BEGIN
IFLOAD='1'THEN
CQI<=DATAIN;
ELSIFCLK'EVENTANDCLK='1'THEN
IFENA='1'THEN
IFCQI="0000"THENCQI<="1001";
ELSECQI<=CQI-'1';ENDIF;
ENDIF;
ENDIF;
ENDPROCESS;
PROCESS(CLK,CQI)IS
BEGIN
IFCLK'EVENTANDCLK='1'THEN
IFCQI="0000"THENCARRY_OUT<='1';
ELSECARRY_OUT<='0';ENDIF;
ENDIF;
ENDPROCESS;
CQ<=CQI;
ENDARCHITECTUREART;
--DCNT6.VHD
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYDCNT6IS
PORT(CLK:
INSTD_LOGIC;
LOAD:
INSTD_LOGIC;
ENA:
INSTD_LOGIC;
DATAIN:
INSTD_LOGIC_VECTOR(3DOWNTO0);
CQ:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
CARRY_OUT:
OUTSTD_LOGIC);
ENDENTITYDCNT6;
ARCHITECTUREARTOFDCNT6IS
SIGNALCQI:
STD_LOGIC_VECTOR(3DOWNTO0);
BEGIN
PROCESS(CLK,LOAD,ENA)IS
BEGIN
IFLOAD='1'THEN
CQI<=DATAIN;
ELSIFCLK'EVENTANDCLK='1'THEN
IFENA='1'THEN
IFCQI="0000"THENCQI<="0101";
ELSECQI<=CQI-'1';ENDIF;
ENDIF;
ENDIF;
ENDPROCESS;
PROCESS(CLK,CQI)IS
BEGIN
IFCLK'EVENTANDCLK='1'THEN
IFCQI="0000"THENCARRY_OUT<='1';
ELSECARRY_OUT<='0';ENDIF;
ENDIF;
ENDPROCESS;
CQ<=CQI;
ENDARCHITECTUREART;
--JSQ.VHD
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
USEIEEE.STD_LOGIC_ARITH.ALL;
ENTITYJSQIS
PORT(COOK:
INSTD_LOGIC;
DATA3:
INSTD_LOGIC_VECTOR(15DOWNTO0);
LOAD:
INSTD_LOGIC;
CLK:
INSTD_LOGIC;
SEC_L:
OUTSTD_LOGIC_VECTOR(3TO0);
SEC_H:
OUTSTD_LOGIC_VECTOR(3TO0);
MIN_L:
OUTSTD_LOGIC_VECTOR(3TO0);
MIN_H:
OUTSTD_LOGIC_VECTOR(3TO0);
DONE:
OUTSTD_LOGIC);
ENDENTITYJSQ;
ARCHITECTUREARTOFJSQIS
COMPONENTDCNT10IS
PORT(CLK,LOAD,ENA:
INSTD_LOGIC;
DATAIN:
INSTD_LOGIC_VECTOR(3DOWNTO0);
CQ:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
CARRY_OUT:
OUTSTD_LOGIC);
ENDCOMPONENTDCNT10;
COMPONENTDCNT6IS
PORT(CLK,LOAD,ENA:
INSTD_LOGIC;
DATAIN:
INSTD_LOGIC_VECTOR(3DOWNTO0);
CQ:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
CARRY_OUT:
OUTSTD_LOGIC);
ENDCOMPONENTDCNT6;
SIGNALNEWCLK:
STD_LOGIC;
SIGNALS1:
STD_LOGIC;
SIGNALS2:
STD_LOGIC;
SIGNALS3:
STD_LOGIC;
SIGNALS4:
STD_LOGIC;
BEGIN
U1:
DCNT10PORTMAP(CLK,LOAD,COOK,DATA3(3DOWNTO0),SEC_L,S1);
U2:
DCNT6PORTMAP(S1,LOAD,COOK,DATA3(7DOWNTO4),SEC_H,S2);
U3:
DCNT10PORTMAP(S2,LOAD,COOK,DATA3(11DOWNTO8),MIN_L,S3);
U4:
DCNT6PORTMAP(S3,LOAD,COOK,DATA3(15DOWNTO12),MIN_H,S4);
DONE<=S1ANDS2ANDS3ANDS4;
ENDARCHITECTUREART;
--YMQ47.VHD
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYYMQ47IS
PORT(AIN4:
INSTD_LOGIC_VECTOR(3DOWNTO0);
DOUT7:
OUTSTD_LOGIC_VECTOR(6DOWNTO0));
ENDENTITYYMQ47;
ARCHITECTUREARTOFYMQ47IS
BEGIN
PROCESS(AIN4)
BEGIN
CASEAIN4IS
WHEN"0000"=>DOUT7<="0111111";--
WHEN"0001"=>DOUT7<="0000110";--1
WHEN"0010"=>DOUT7<="1011011";--2
WHEN"0011"=>DOUT7<="1001111";--3
WHEN"0100"=>DOUT7<="1100110";--4
WHEN"0101"=>DOUT7<="1101101";--5
WHEN"0110"=>DOUT7<="1111101";--6
WHEN"0111"=>DOUT7<="0000111";--7
WHEN"1000"=>DOUT7<="1111111";--8
WHEN"1001"=>DOUT7<="1101111";--9
WHEN"1010"=>DOUT7<="1011110";--d
WHEN"1011"=>DOUT7<="1011100";--o
WHEN"1100"=>DOUT7<="1010100";--n
WHEN"1101"=>DOUT7<="1111001";--E
WHENOTHERS=>DOUT7<="0000000";
ENDCASE;
ENDPROCESS;
ENDARCHITECTUREART;
--WBLKZQ.VHD
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
USEIEEE.STD_LOGIC_ARITH.ALL;
ENTITYWBLKZQIS
PORT(RESET1,SET_T1,START1,TEST1,CLKIN:
INSTD_LOGIC;
MODE:
INSTD_LOGIC_VECTOR(1DOWNTO0);
DATA0:
INSTD_LOGIC_VECTOR(15DOWNTO0);
PWM,COOK1:
OUTSTD_LOGIC;
SEC_L1,SEC_H1,MIN_L1,MIN_H1:
OUTSTD_LOGIC_VECTOR(6DOWNTO0));
ENDENTITYWBLKZQ;
ARCHITECTUREARTOFWBLKZQIS
COMPONENTKZQIS
PORT(RESET,SET_T,START,TEST,CLK,DONE:
INSTD_LOGIC;
COOK,LD_8888,LD_CLK,LD_DONE:
OUTSTD_LOGIC);
ENDCOMPONENTKZQ;
COMPONENTPKZQIS
PORT(ENA,CLK:
INSTD_LOGIC
MODE0:
INSTD_LOGIC_VECTOR(1DOWNTO0);
POUT:
OUTSTD_LOGIC);
ENDCOMPONENTPKZQ;
COMPONENTZZQIS
PORT(LD_8888,LD_CLK,LD_DONE:
INSTD_LOGIC;
DATA1:
INSTD_LOGIC_VECTOR(15DOWNTO0);
LOAD:
OUTSTD_LOGIC;
DATA2:
OUTSTD_LOGIC_VECTOR(15DOWNTO0));
ENDCOMPONENTZZQ;
COMPONENTJSQIS
PORT(CLK,COOK,LOAD:
INSTD_LOGIC;
DATA3:
INSTD_LOGIC_VECTOR(15DOWNTO0);
DONE:
OUTSTD_LOGIC;
SEC_L,SEC_H,MIN_L,MIN_H:
OUTSTD_LOGIC_VECTOR(3DOWNTO0));
ENDCOMPONENTJSQ;
COMPONENTYMQ47IS
PORT(AIN4:
INSTO_LOGIC_VECTOR(3DOWNTO0);
DOUTT:
OUTSTD_LOGIC_VECTOR(6DOWNTO0));
ENDCOMPONENTYMQ47;
SIGNALS2:
STD_LOGIC;
SIGNALS3:
STD_LOGIC;
SIGNALS4:
STD_LOGIC_VECTOR(15DOWNTO0);
SIGNALS5:
STD_LOGIC;
SIGNALS6:
STD_LOGIC;
SIGNALS7:
STD_LOGIC;
SIGNALS8:
STD_LOGIC;
SIGNALS9:
STD_LOGIC_VECTOR(3DOWNTO0);
SIGNALS10:
STD_LOGIC_VECTOR(3DOWNTO0);
SIGNALS11:
STD_LOGIC_VECTOR(3DOWNTO0);
SIGNALS12:
STD_LOGIC_VECTOR(3DOWNTO0);
BEGIN
U1:
KZQPORTMAP(RESET1,SET_T1,START1,TEST1,CLKIN,S3,S2,S6,S7,S8);
U2:
PKZQPORTMAP(S2,CLKIN,MODE0(1DOWNTO0),PWM);
U3:
ZZQPORTMAP(S6,S7,S8,DATA0(15DOWNTO0),S5,S4(15DOWNTO0));
U4:
JSQPORTMAP(CLKIN,S2,S5,S4(15DOWNTO0),S3,S9(3DOWNTO0),S10(3DOWNTO0),S11(3DOWNTO0),S12(3DOWNTO0));
U5:
YMQ47PORTMAP(S9(3DOWNTO0),SEC_L1(6DOWNTO0));
U6:
YMQ47PORTMAP(S10(3DOWNTO0),SEC_H1(6DOWNTO0));
U7:
YMQ47PORTMAP(S11(3DOWNTO0),MIN_L1(6DOWNTO0));
U8:
YMQ47PORTMAP(S12(3DOWNTO0),MIN_H1(6DOWNTO0));
COOK1<=S2;
ENDARCHITECTUERART;
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