pci引脚定义pci接口定义.docx
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- 上传时间:2023-03-29
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- 页数:8
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pci引脚定义pci接口定义.docx
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pci引脚定义pci接口定义
pci引脚定义
Pin
+5V
+3.3V
Universal
Description
A1
TRST
TestLogicReset
A2
+12V
+12VDC
A3
TMS
TestMdeSelect
A4
TDI
TestDataInput
A5
+5V
+5VDC
A6
INTA
InterruptA
A7
INTC
InterruptC
A8
+5V
+5VDC
A9
RESV01
ReservedVDC
A10
+5V
+3.3V
SignalRail
+VI/O(+5Vor+3.3V)
A11
RESV03
ReservedVDC
A12
GND03
(OPEN)
(OPEN)
GroundorOpen(Key)
A13
GND05
(OPEN)
(OPEN)
GroundorOpen(Key)
A14
RESV05
ReservedVDC
A15
RESET
Reset
A16
+5V
+3.3V
SignalRail
+VI/O(+5Vor+3.3V)
A17
GNT
GrantPCIuse
A18
GND08
Ground
A19
RESV06
ReservedVDC
A20
AD30
Address/Data30
A21
+3.3V01
+3.3VDC
A22
AD28
Address/Data28
A23
AD26
Address/Data26
A24
GND10
Ground
A25
AD24
Address/Data24
A26
IDSEL
InitializationDeviceSelect
A27
+3.3V03
+3.3VDC
A28
AD22
Address/Data22
A29
AD20
Address/Data20
A30
GND12
Ground
A31
AD18
Address/Data18
A32
AD16
Address/Data16
A33
+3.3V05
+3.3VDC
A34
FRAME
AddressorDataphase
A35
GND14
Ground
A36
TRDY
TargetReady
A37
GND15
Ground
A38
STOP
StopTransferCycle
A39
+3.3V07
+3.3VDC
A40
SDONE
SnoopDone
A41
SBO
SnoopBackoff
A42
GND17
Ground
A43
PAR
Parity
A44
AD15
Address/Data15
A45
+3.3V10
+3.3VDC
A46
AD13
Address/Data13
A47
AD11
Address/Data11
A48
GND19
Ground
A49
AD9
Address/Data9
A52
C/BE0
mand,ByteEnable0
A53
+3.3V11
+3.3VDC
A54
AD6
Address/Data6
A55
AD4
Address/Data4
A56
GND21
Ground
A57
AD2
Address/Data2
A58
AD0
Address/Data0
A59
+5V
+3.3V
SignalRail
+VI/O(+5Vor+3.3V)
A60
REQ64
Request64bit?
?
?
A61
VCC11
+5VDC
A62
VCC13
+5VDC
A63
GND
Ground
A64
C/BE[7]#
mand,ByteEnable7
A65
C/BE[5]#
mand,ByteEnable5
A66
+5V
+3.3V
SignalRail
+VI/O(+5Vor+3.3V)
A67
PAR64
Parity64?
?
?
A68
AD62
Address/Data62
A69
GND
Ground
A70
AD60
Address/Data60
A71
AD58
Address/Data58
A72
GND
Ground
A73
AD56
Address/Data56
A74
AD54
Address/Data54
A75
+5V
+3.3V
SignalRail
+VI/O(+5Vor+3.3V)
A76
AD52
Address/Data52
A77
AD50
Address/Data50
A78
GND
Ground
A79
AD48
Address/Data48
A80
AD46
Address/Data46
A81
GND
Ground
A82
AD44
Address/Data44
A83
AD42
Address/Data42
A84
+5V
+3.3V
SignalRail
+VI/O(+5Vor+3.3V)
A85
AD40
Address/Data40
A86
AD38
Address/Data38
A87
GND
Ground
A88
AD36
Address/Data36
A89
AD34
Address/Data34
A90
GND
Ground
A91
AD32
Address/Data32
A92
RES
Reserved
A93
GND
Ground
A94
RES
Reserved
B1
-12V
-12VDC
B2
TCK
TestClock
B3
GND
Ground
B4
TDO
TestDataOutput
B5
+5V
+5VDC
B6
+5V
+5VDC
B7
INTB
InterruptB
B8
INTD
InterruptD
B9
PRSNT1
Reserved
B10
RES
+VI/O(+5Vor+3.3V)
B11
PRSNT2
?
?
B12
GND
(OPEN)
(OPEN)
GroundorOpen(Key)
B13
GND
(OPEN)
(OPEN)
GroundorOpen(Key)
B14
RES
ReservedVDC
B15
GND
Reset
B16
CLK
Clock
B17
GND
Ground
B18
REQ
Request
B19
+5V
+3.3V
SignalRail
+VI/O(+5Vor+3.3V)
B20
AD31
Address/Data31
B21
AD29
Address/Data29
B22
GND
Ground
B23
AD27
Address/Data27
B24
AD25
Address/Data25
B25
+3.3V
+3.3VDC
B26
C/BE3
mand,ByteEnable3
B27
AD23
Address/Data23
B28
GND
Ground
B29
AD21
Address/Data21
B30
AD19
Address/Data19
B31
+3.3V
+3.3VDC
B32
AD17
Address/Data17
B33
C/BE2
mand,ByteEnable2
B34
GND13
Ground
B35
IRDY
InitiatorReady
B36
+3.3V06
+3.3VDC
B37
DEVSEL
DeviceSelect
B38
GND16
Ground
B39
LOCK
Lockbus
B40
PERR
ParityError
B41
+3.3V08
+3.3VDC
B42
SERR
SystemError
B43
+3.3V09
+3.3VDC
B44
C/BE1
mand,ByteEnable1
B45
AD14
Address/Data14
B46
GND18
Ground
B47
AD12
Address/Data12
B48
AD10
Address/Data10
B49
GND20
Ground
B50
(OPEN)
GND
(OPEN)
GroundorOpen(Key)
B51
(OPEN)
GND
(OPEN)
GroundorOpen(Key)
B52
AD8
Address/Data8
B53
AD7
Address/Data7
B54
+3.3V12
+3.3VDC
B55
AD5
Address/Data5
B56
AD3
Address/Data3
B57
GND22
Ground
B58
AD1
Address/Data1
B59
VCC08
+5VDC
B60
ACK64
Acknowledge64bit?
?
?
B61
VCC10
+5VDC
B62
VCC12
+5VDC
B63
RES
Reserved
B64
GND
Ground
B65
C/BE[6]#
mand,ByteEnable6
B66
C/BE[4]#
mand,ByteEnable4
B67
GND
Ground
B68
AD63
Address/Data63
B69
AD61
Address/Data61
B70
+5V
+3.3V
SignalRail
+VI/O(+5Vor+3.3V)
B71
AD59
Address/Data59
B72
AD57
Address/Data57
B73
GND
Ground
B74
AD55
Address/Data55
B75
AD53
Address/Data53
B76
GND
Ground
B77
AD51
Address/Data51
B78
AD49
Address/Data49
B79
+5V
+3.3V
SignalRail
+VI/O(+5Vor+3.3V)
B80
AD47
Address/Data47
B81
AD45
Address/Data45
B82
GND
Ground
B83
AD43
Address/Data43
B84
AD41
Address/Data41
B85
GND
Ground
B86
AD39
Address/Data39
B87
AD37
Address/Data37
B88
+5V
+3.3V
SignalRail
+VI/O(+5Vor+3.3V)
B89
AD35
Address/Data35
B90
AD33
Address/Data33
B91
GND
Ground
B92
RES
Reserved
B93
RES
Reserved
B94
GND
Ground
pci接口定义
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