EDA汇总Verilog HDL编程.docx
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EDA汇总Verilog HDL编程.docx
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EDA汇总VerilogHDL编程
【例4.8】BCD码加法器
moduleadd4_bcd(cout,sum,ina,inb,cin);
inputcin;input[3:
0]ina,inb;
output[3:
0]sum;reg[3:
0]sum;
outputcout;regcout;
reg[4:
0]temp;
always@(ina,inb,cin)
begintemp<=ina+inb+cin;
if(temp>9)(cout,sum)<=temp+6;
else(cout,sum)<=temp;
end
endmodule
【例4.10】带同步清0/同步置1(低电平有效)的D触发器
moduledff_syn(q,qn,d,clk,set,reset);
inputd,clk,set,reset;outputregq,qn;
always@(posedgeclk)
begin
if(~reset)beginq<=1’b0;qn<=1’b1;end
elseif(~set)beginq<=1’b1;qn<=1’b0;end
elsebeginq<=d;qn<=~d;end
end
endmodule
【例4.11】带异步清0/异步置1(低电平有效)的D触发器
moduledff_asyn(q,qn,d,clk,set,reset);
inputd,clk,set,reset;outputregq,qn;
always@(posedgeclkornegedgesetornegedgereset)
begin
if(~reset)beginq<=1’b0;qn<=1’b1;end
elseif(~set)beginq<=1’b1;qn<=1’b0;end
elsebeginq<=d;qn<=~d;end
end
endmodule
【例4.13】4位计数器的仿真代码
`timescale1ns/1ns
`include“count4.v”
modulecoun4_tp;
regclk,reset;
wire[3:
0]out;
parameterDELY=100;
count4mycount(out,reset,clk);
always#(DELY/2)clk=~clk;
initial
beginclk=0;reset=0;
#DELYreset=1;
#DELYreset=0;
#(DELY*20)$finish;end
initial$monitor($time,,”clk=%dreset=%dout=%d,clk,reset,out);
endmodule
【例4.14】带同步复位的4位模10BCD码计数器
modulecount10(cout,qout,reset,clk);
inputreset,clk;outputreg[3:
0]qout;outputcout;
always@(posedgeclk)
begin
if(reset)qout<=0;
elseif(qout<9)qout<=qout+1;
elseqout<=0;
end
assigncout=(qout==9)?
1:
0;
endmodule
【例6.1】用case语句描述的4选1数据选择器
modulemux4_1(out,in0,in1,in2,in3,se1);
inputin0,in1,in2,in3;
input[1:
0]se1;outputregout;
always@(in0orin1orin2orin3orse1)
case(se1)
2’b00:
out=in0;
2’b01:
out=in1;
2’b10:
out=in2;
2’b11:
out=in3;
default:
out=2’box;
endcase
endmodule
【例6.2】同步置数、同步清零的计数器
modulecount(out,data,load,reset,clk);
inputload,clk,reset;input[7:
0]data;outputreg[7:
0]out;
always@(posedgeclk)
begin
if(!
reset)out<=8’h00;
elseif(load)out=data;
elseout<=out+1;
end
endmodule
【例6.4】用initial过程语句对测试变量赋值
’timescale1ns/1ns
moduletest;
rega,b.c;
initialbegina=0;b=1;c=0;
#50a=1;b=0;
#50a=0;c1;
#50b=1;
#50b=0;c=0;
#50$finish;end
endmodule
【例6.5】用begin-end串行块产生信号波形
’timescale10ns/1ns
modulewave1;
parameterCYCLE=10;
regwave;
initial
beginwave=0;
#(CYCLE/2)wave=1;
#(CYCLE/2)wave=0;
#(CYCLE/2)wave=1;
#(CYCLE/2)wave=0;
#(CYCLE/2)wave=1;
#(CYCLE/2)$stop;
end
initial$monitor($time,,,”wave=%b”,wave);
endmodule
【例6.15】模为60的8421BCD码加法计数器
modulecount60(qout,cout,data,load,reset,clk);
inputload,clk,reset;input[7:
0]data;
outputreg[7:
0]qout;outputcout;
always@(posedgeclk)
begin
if(reset)qout<=0;
elseif(load)qout<=data;
elsebegin
if(qout[3:
0]==9)
beginqout[3:
0]<=0;
if(qout[7:
4]==5)qout[7:
4]<=0;
elseqout[7:
4]<=qout[7:
4]+1;
end
elseqout[3:
0]<=qout[3:
0]+1;
end
end
assigncout=(qout==8’d59)?
1:
0;
endmodule
【例6.17】BCD码——7段数码管译码器
moduledecode4_7(a,b,c,d,e,f,g,D3,D2,D1,D0);
inputD3,D2,D1,D0;
outputrega,b,c,d,e,f,g;
always@(*)
begin
case({D3,D2,D1,D0})
4’d0:
{a,b,c,d,e,f,g}=7’b1111110;
4’d1:
{a,b,c,d,e,f,g}=7’b0110000;
4’d2:
{a,b,c,d,e,f,g}=7’b1101101;
4’d3:
{a,b,c,d,e,f,g}=7’b1111001;
4’d4:
{a,b,c,d,e,f,g}=7’b0110011;
4’d5:
{a,b,c,d,e,f,g}=7’b1011011;
4’d6:
{a,b,c,d,e,f,g}=7’b1011111;
4’d7:
{a,b,c,d,e,f,g}=7’b1110000;
4’d8:
{a,b,c,d,e,f,g}=7’b1111111;
4’d9:
{a,b,c,d,e,f,g}=7’b1111011;
default:
{a,b,c,d,e,f,g}=7’b1111110;
endcase
end
endmodule
【例6.18】用case语句描述的下降沿触发的JK触发器
modulejk_ff(clk,j,k,q);
inputclk,j,k;outputregq;
always@(negedgeclk)
begin
case({j,k})
2’b00:
q<=q;
2’b01:
q<=1’b0;
2’b10:
q<=1’b1;
2’b11:
q<=~q;
endcase
end
endmodule
例6.36用ifelse描述的模12分频器
modulefdivi12(teset,clkin,clkout,qout);
inputreset,clkin:
outputregclkout;outputreg[4:
0]qout;
always@(posedgeclkin)
begin
if(!
reset)
begin
clkout<=0;qout<=0;
end
elesbegin
if(qout==5)
begin
qout<=0;clkout<=~clkout:
end
elseqout<=qout+1;
end
end
endmodule
例6.37模12分频器
modulefdivi12(teset,clkin,clkout,qout);
inputreset,clkin:
outputregclkout;outputreg[4:
0]qout;
always@(posedgeclkin)
begin
if(!
reset)qout<=0;
elseif(qout<11)qout<+qout+1;
elseqout<=0;
end
always@(posedgeclkin)
begin
if(!
reset)clkout<=0;
elseif(qout==11)clkout<=1;
elseclkout<=0;
end
endmodule
例6.38.模12分频器
modulefdivi12(teset,clkin,clkout,qout);
inputreset,clkin:
outputregclkout;outputreg[4:
0]qout;
always@(posedgeclkin)
begin
if(!
reset)qout<=0;
elseif(qout<11)qout<+qout+1;
elseqout<=0;
end
assignclkout=(qout==11)?
:
0;
endmodule
例7.2用case语句描述的4选1mux
modulemux4_1b(out,in1,in2,in3,in4,s0,s1);
inputin1,in2,in3,in4,s0,s1;outputregout;
always@(*)
case({s0,s1})
2'b00:
out=in1;
2'b01:
out=in2;
2'b10:
out=in3;
2'b11:
out=in4;
default:
out=2'bx;
endcase
endmodule
例8.1用状态机设计模5计数器
modulefam(clk,clr,z,qout);
inputclk,clr;outputregz;outputreg[2:
0]qout;
always@(posedgeclkorposedgeclr)
beginif(clr)qout<=0;
elsecase(qout)
3'b000:
qout<=3'b001;
3'b001:
qout<=3'b010;
3'b010:
qout<=3'b011;
3'b011:
qout<=3'b100;
3'b100:
qout<=3'b000;
default:
qout<=3'b000;
endcase
end
always@(qout)
begincase(qout)
3'b100:
z=1'b1;
default:
z=1'b0;
endcase
end
endmodule
例8.2用状态机设计模5计数器(单过程描述)。
modulefsm1(clk,clr,z,qout);
inputclk,clr;outputregz;outputreg[2:
0]qout;
always@(posedgeclkorposedgeclr)
beginif(clr)qout<=0;
elsecase(qout)
3'b000:
beginqout<=3'b001;z=1'b0;end
3'b001:
beginqout<=3'b010;z=1'b0;end
3'b010:
beginqout<=3'b011;z=1'b0;end
3'b011:
beginqout<=3'b100;z=1'b0;end
3'b100:
beginqout<=3'b000;z=1'b1;end
default:
beginqout<=3'b000;z=1'b0;end
endcase
end
endmodule
例8.3"101"序列检测器的描述(cs,ns,ol各用一个过程描述)
modulefsm1_set101(clk,clr,x,z);
inputclk,clr,x;outputregz;reg[10]state,next_state;
parameters0=2'b00,s1=2'b01,s2=2'b11,s3=2'b10;
/*状态编码,采用格雷编码方式*/
always@(posedgeclkorposedgeclr)
beginif(clr)state<=s0;
elsestate<=next_state;
end
always@(stateorx)
begin
case(state)
s0:
beginif(x)next_state<=s1;
elsenext_state<=s0;end
s1:
beginif(x)next_state<=s1;
elsenext_state<=s2;end
s2:
beginif(x)next_state<=s3;
elsenext_state<=s0;end
s2:
beginif(x)next_state<=s1;
elsenext_state<=s2;end
default:
next_state<=s0;
endcase
end
always@(state)
begincase(state)
s3=:
z=1'b1;
default:
z=1'b0;
endcase
end
endmodule
例8.4采用两个过程对"101"序列检测器进行描述(cs+ns,ol双过程描述)
modulefsm2_set101(clk,clr,x,z);
inputclk,clr,x;outputregz;reg[10]state;
parameters0=2'b00,s1=2'b01,s1=2'b11,s3=2'b10;
/*状态编码,采用格雷编码方式*/
always@(posedgeclkorposedgeclr)
beginif(clr)state<=s0;
elsestate<=state;
end
always@(stateorx)
begin
case(state)
s0:
beginif(x)state<=s1;
elsestate<=s0;end
s1:
beginif(x)state<=s1;
elsestate<=s2;end
s2:
beginif(x)state<=s3;
elsestate<=s0;end
s2:
beginif(x)state<=s1;
elsestate<=s2;end
default:
state<=s0;
endcase
end
always@(state)
begincase(state)
s3:
z=1'b1;
default:
z=1'b0;
endcase
end
endmodule
例8.5"101"序列检测器(CS,NS+OL双过程描述)。
modulefsm3_seq101(clk,clr,x,z);
inputclk,clr,x;outputregz;reg[1:
0]state,next_state;
parameterS0=2'b00,S1=2'b01,S2=2'b11,S3=2'b10;
always@(posedgeclkorposedgeclr)
beginif(clr)state<=S0;
elsestate<=next_state;
end
always@(stateorx)
begincase(state)
S0:
beginif(x)beginnext_state<=S1;z=1'b0;end
elsebeginnext_state<=S0;z=1'b0;end
end
S1:
beginif(x)beginnext_state<=S1;z=1'b0;end
elsebeginnext_state<=S2;z=1'b0;end
end
S2:
beginif(x)beginnext_state<=S3;z=1'b0;end
elsebeginnext_state<=S0;z=1'b0;end
end
S3:
beginif(x)beginnext_state<=S1;z=1'b0;end
elsebeginnext_state<=S2;z=1'b0;end
end
default:
beginnext_state<=S0;z=1'b0;end
endcase
end
endmodule
例8.6"101"序列检测器(CS+NS+OL单过程描述)。
modulefsm4_seq101(clk,clr,x,z);
inputclk,clr,x;outputregz;reg[1:
0]state;
parameterS0=2'b00,S1=2'b01,S2=2'b11,S3=2'b10;
always@(posedgeclkorposedgeclr)
beginif(clr)state<=S0;
elsecase(state)
S0:
beginif(x)beginstate<=S1;z=1'b0;end
elsebeginstate<=S0;z=1'b0;end
end
S1:
beginif(x)beginstate<=S1;z=1'b0;end
elsebeginstate<=S2;z=1'b0;end
end
S2:
beginif(x)beginstate<=S3;z=1'b0;end
elsebeginstate<=S0;z=1'b0;end
end
S3:
beginif(x)beginstate<=S1;z=1'b0;end
elsebeginstate<=S2;z=1'b0;end
end
default:
beginstate<=S0;z=1'b0;end
endcase
end
endmodule
例8.7"1111"序列检测器的Verilog描述(单过程描述CS+NS+OL)
modulefsm_seq1111(x,z,clk,reset);
inputx,clk,reset;
outputregz;
reg[4:
0]state;
parameters0='d0,s1='d1,s2='d2,s3='d3,s4='d4;
always@(posedgeclk)
beginif(reset)beginstate<=s0;z<0;end
elsecasex(state)
s0:
beginif(x==0)beginstate<=s0;z<=0;end
elsebeginstate<=s1;z<=0;end
end
s1:
beginif(x==0)beginstate<=s0;z<=0;end
elsebeginstate<=s2;z<=0;end
end
s2:
beginif(x==0)beginstate<=s0;z<=0;end
elsebeginstate<=s3;z<=0;end
end
s3:
beginif(x==0)beginstate<=s0;z<=0;end
elsebeginstate<=s4;z<=0;end
end
s4:
beginif(x==0)beginstate<=s0;z<=0;end
elsebeginstate<=s4;z<=0;end
end
default:
state<=s0;
endcase
end
endmodule
例8.10用有限状态机设计除法电路
moduledivision(a,b,clk,result,yu);
input[3:
0]a,b;
outputreg[3:
0]result,yu;
inputclk;reg[1:
0]state;reg[3:
0]m,n;
parameters0=2'b00,s1=2'b01,s2=2'b10;
always@(posedgeclk)
begincase(state)
s0:
beginif(a>=b)beginn<=a-b;m<=4'b0001;state<=s1;end
elsebeginm<=4'b0000;n<=a;state<=s2;end
end
s1:
beginif(n>=b)beginm<=m+1;n<=n-b;state<=s1;end
elsebeginstate<=s2;end
end
s2:
beginresult<=m;yu<=n;state<=s0;end
default:
state<=s0;
endcase
end
endmodule
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