触发器设计Word下载.docx
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触发器设计Word下载.docx
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)then
q_temp<
else
=q_temp;
qb_temp<
=qb_temp;
endif;
endprocess;
q<
qb<
endrtl;
2主从JK触发器的设计
源程序:
entityjkffis
port(j,k,cp,r,s:
q,pb:
endjkff;
architecturertlofkffis
signalq_temp,qb_temp:
std_logic;
process(j,k,cp)
begin
if(r='
ands='
elsif(r='
ands='
elsif(cp'
eventandcp='
if(j='
andk='
=notq_temp;
=notqb_temp;
endif;
3,D触发器的设计
usreieee.std_logic)_1164.all;
entitydffis
port(d,cp,r,s:
enddff;
architecturertlofdffis
process(cp)
begin
=d;
=notd;
endif
寄存器的设计
usrieee.std_logic_1164.all;
entityjcqis
port(clk:
r:
d:
instd_logic_vector(3dowmto0);
q:
outstd_logic_vector(3downto0);
endjcq;
architecturertllfjcqis
signalq_temp:
std_logic_vecter(3dowmto0);
process(clk,r)
if(r='
="
0000"
elsif(clk'
eventandclk='
4.2
双向移位寄存器的设计
packageshift_typeis
subtypestd4isstd_logic_vector(3downto0);
endshift_type;
usework.shift_type.all;
entiytywjcqis
port(din:
instd4;
clk,load,left_right:
dout:
inoutstd4);
endywjcq;
architecturertllfywjcqis
signalshift_val:
std4;
nxt:
process(load,left_right,din,dout)
ifload='
then
shift_val<
=din;
elsifleft_right='
shift_val(2downto0)<
=dout(3downto1);
shift_val(3)<
else
shift_val(3downto1)<
=dout(2downto0);
shift_val(0)<
endif
endprocessnxt;
current:
process(clk)
ifclk'
then
dout<
=shift_val;
endprocesscurrent;
4.3,4位同步二进制计数器的设计
源程序;
useieee.std_logic_unsigned.all;
entityb19is
port(cp,r,ld,ep,et:
instd_logic_vector(3downto0);
c:
outstd_logic;
endb19;
architectureb19_arcofb19is
process(cp,r,ld,ep)
variabletmp:
std_logic_vector(3downto0);
ifr='
tmp:
elsifvp'
ifld='
elsifep='
andet='
iftmp="
1111"
c<
q<
=tmp;
ednprocess;
endb19_arc;
4.4。
单时钟同步十六进制加/减计数器的设计
源程序:
entityls191is
prot(cp,s,ld,ud,d0,d1,d2,d3:
endls191;
architecturertlofls191is
signaly,d:
process(cp,s,ldud)
d<
=d3&
d2&
d1&
d0;
if(ld='
y<
elsitf(cp'
ifs='
ifud='
if(y="
=y+1;
elsifud='
=y-1;
elsifs='
=y;
endprocess;
4.5双时钟同步十六进制加/减计数器的设计
entityb21addis
port(clk1,ld,r:
co:
outstd_logic_vector(3downto0));
endb21add;
architectureb21_arcofb21addis
process(clk1,ld,r)
variabletmpLstd_logic_vector(3downto0);
bigin
co<
elsifld='
elsifclk1'
eventandclk1='
=tmp+1;
endb21_arc;
B21SUB.VHD
entityb21subis
port(clk1,ld,r:
endb21sub;
B21B.VHD
endb21bis;
port(sel:
d1,d0:
endb21b;
architectureb21_arcofb21bis
=d1whensel='
else
d0;
endb21b_arc;
BUS21A.VHD
entitybUS21ais
port(sel:
endbus21a;
architectureb21_arcofbus21ais
4.6同步十进制加法计数器的设计
entity1s160is
port(cp,rd,ld,ep,et,d0,d1,d2,d3:
y:
end1s160;
architecturertlof1s160is
signald,q:
process(cp,rd,ld,ep,et)
ifrd='
elsif(cp'
elsif(ep='
andcp='
=q;
elsif(et='
elsif(q=9)then;
=q+1;
y<
4.7单时钟,同步十进制可逆计数器的设计
entity1s190is
port(cp,s,ld,ud,d0,d1,d2,d3:
end1s190;
architecturertlof1s190is
signaly,d:
process(cp,s,ld,ud)
1001"
if(y='
0000'
4.8异步二进制加法计数器的设计
entity1s293is
port(cp,rd,:
end1s293;
architecturertlof1s293is
process(cp)
if(cp'
4.9同步100进制计数器的设计
useieee.std_logic_arith.all;
entityh27is
port(clk:
qa:
qb:
endh27;
architecturertlofh27is
signalqan:
signalqbn:
signalcin:
ifqan=9then
qan<
cin<
=qan+1;
ptovrss(clk,cin)
ifcin='
ifqbn=9then
qbn<
=qbn+1;
qa<
=qan;
=qbn;
4.10同步
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