英语I2C总线规范21部分.docx
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英语I2C总线规范21部分.docx
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英语I2C总线规范21部分
THEI2C-BUSSPECIFICATIONVERSION2.1
JANUARY2000
11EXTENSIONSTOTHESTANDARD-MODEI2C-BUSSPECIFICATION
TheStandard-modeI2C-busspecification,withitsdatatransferrateofupto100kbit/sand7-bitaddressing,hasbeeninexistencesincethebegniingofthe1980's.ThisconceptrapidlygrewinpopularityandistodayacceptedworldwideasadefactostandardwithseveralhundreddifferentcompatibleICsonofferfromPhilipsSemiconductorsandothersuppliers.Tomeetthedemandsforhigherspeeds,aswellasmakeavailablemoreslaveaddressforthegrowingnumberofnewdevices,theStandard-modeI2C-busspecificationwasupgradedovertheyearsandtodayisavailablewiththefollowingextensions:
-mode,withabitrateupto400kbit/s.
-speedmode(Hs-mode),withabitrateupto3.4Mbit/s.
-bitaddressing,whichallowstheuseofupto1024additionalslaveaddresses.
TherearetwomainreasonsforextendingtheregularI2C-busspecification:
dtotransferlargeamountsofserialdataandrequirebitratesfarinexcessof100kbit/s(Standard-mode),oreven400kbit/s(Fast-mode).Asaresultofcontinuingimprovementsinsemiconductortechnologies,I2C-busdevicesarenowavailablewithbitratesofupto3.4Mbit/s(Hs-mode)withoutanynoticeableincreasesinthemanufacturing
costoftheinterfacecircuitry.
-bitaddressingschemeweresoonallocated,itbecameapparentthatmoreaddresscombinationswererequiredtopreventproblemswiththeallocationofslaveaddressesfornewdevices.Thisproblemwasresolvedwiththenew10-bitaddressingscheme,whichallowedaboutatenfoldincreaseinavailableaddresses.
NewslavedeviceswithaFast-orHs-modeI2C-businterfacecanhavea7-ora10-bitslaveaddress.Ifpossible,a7-bitaddressispreferredasitisthecheapest
hardwaresolutionandresultsintheshortestmessagelength.Deviceswith7-and10-bitaddressescanbemixedinthesameI2C-bussystemregardlessofwhetheritisanF/S-orHs-modesystem.Bothexistingandfuturemasterscangenerateeither7-or10-bitaddresses.
12FAST-MODE
WiththeFast-modeI2C-busspecification,theprotocol,format,logiclevelsandmaximumcapacitiveloadfortheSDAandSCLlinesquotedintheStandard-modeI2C-busspecificationareunchanged.NewdeviceswithanI2C-businterfacemustmeetatleasttheminimumrequirementsoftheFast-orHs-modespecification(seeSection13).
Fast-modedevicescanreceiveandtransmitatupto400kbit/s.Theminimumrequirementisthattheycansynchronizewitha400kbit/stransfer;theycanthenprolongtheLOWperiodoftheSCLsignaltoslowdownthetransfer.Fast-modedevicesaredownward-compatibleandcancommunicatewithStandard-modedevicesina0to100kbit/sI2C-bussystem.AsStandard-modedevices,however,arenotupwardcompatible,theyshouldnotbeincorporatedinaFast-modeI2C-bussystemastheycannotfollowthehighertransferrateand
unpredictablestateswouldoccur.
TheFast-modeI2C-busspecificationhasthefollowingadditionalfeaturescomparedwiththeStandard-mode:
adapted.ThereisnoneedforcompatibilitywithotherbussystemssuchasCBUSbecausetheycannotoperateattheincreasedbitrate.
-modedevicesincorporatespikesuppressionandaSchmitttriggerattheSDAandSCLinputs.
-modedevicesincorporateslopecontrolofthefallingedgesoftheSDAandSCLsignals.
-modedeviceisswitchedoff,theSDAand
SCLI/Opinsmustbefloatingsothattheydon'tobstructtbhueslines.
-updevicesconnectedtothebuslinesmustbeadaptedtoaccommodatetheshortermaximumpermissiblerisetimefortheFast-modeI2C-bus.Forbusloadsupto200pF,thepull-updeviceforeachbuslinecanbearesistor;forbusloadsbetween200pFand400pF,thepull-updevicecanbeacurrentsource(3mAmax.)oraswitchedresistorcircuit(seeFig.43).
13Hs-MODE
High-speedmode(Hs-mode)devicesofferaquantumleapinI2C-bustransferspeeds.Hs-modedevicescantransferinformationatbitratesofupto3.4Mbit/s,yettheyremainfullydownwardcompatiblewithFast-orStandard-mode(F/S-mode)devicesforbi-directionalcommunicationinamixed-speedbussystem.WiththeexceptionthatarbitrationandclocksynchronizationisnotperformedduringtheHs-modetransfer,thesameserialbusprotocolanddataformatismaintainedaswiththeF/S-modesystem.Dependingontheapplication,newdevicesmayhaveaFastorHs-modeI2C-businterface,althoughHs-modedevicesarepreferredastheycanbedesigned-intoagreaternumberofapplications.
13.1Highspeedtransfer
Toachieveabittransferofupto3.4Mbit/sthefollowingimprovementshavebeenmadetotheregularI2C-busspecification:
-modemasterdeviceshaveanopen-drainoutputbufferfortheSDAHsignalandacombinationofanopen-drainpull-downandcurrent-sourcepull-upcircuitontheSCLHoutput
(1).Thiscurrent-sourcecircuitshortenstherisetimeoftheSCLHsignal.Onlythecurrent-sourceofonemasterisenabledatanyonetime,andonlyduringHs-mode.
duringHs-modetransferinmulti-mastersystems,whichspeeds-upbithandlingcapabilities.ThearbitrationprocedurealwaysfinishesafteraprecedingmastercodetransmissioninF/S-mode.
-modemasterdevicesgenerateaserialclocksignalwithaHIGHtoLOWratioof1to2.Thisrelievesthetimingrequirementsforset-upandholdtimes.
-modemasterdevicescanhaveabuilt-inbridge
(1).DuringHs-modetransfer,thehighspeeddata(SDAH)andhigh-speedserialclock(SCLH)linesofHs-modedevicesareseparatedbythisbridgefromtheSDAandSCLlinesofF/S-modedevices.ThisreducesthecapacitiveloadoftheSDAHandSCLHlinesresultinginfasterriseandfalltimes.
-modeslavedevicesandF/S-modeslavedevicesisthespeedatwhichtheyoperate.Hs-modeslaveshaveopen-drainoutputbuffersontheSCLHandSDAHoutputs.Optionalpull-downtransistorsontheSCLHpincanbeusedtostretchtheLOWleveloftheSCLHsignal,althoughthisisonlyallowedaftertheacknowledgebitinHs-modetransfers.
-modedevicesincorporatespikesuppressionandaSchmitttriggerattheSDAHandSCLHinputs.
-modedevicesincorporateslopecontrolofthefallingedgesoftheSDAHandSCLHsignals.
Figure20showsthephysicalI2C-busconfigurationinasystemwithonlyHs-modedevices.PinsSDAandSCLonthemasterdevicesareonlyusedinmixed-speedbussystemsandarenotconnectedinanHs-modeonlysystem.Insuchcases,thesepinscanbeusedforother
functions.
OptionalseriesresistorsRsprotecttheI/OstagesoftheI2C-busdevicesfromhigh-voltagespikesonthebuslinesandminimizeringingandinterference.
Pull-upresistorsRpmaintaintheSDAHandSCLHlinesataHIGHlevelwhenthebusisfreeandensurethesignalsarepulledupfromaLOWtoaHIGHlevelwithintherequiredrisetime.Forhighercapacitivebus-lineloads(>100pF),theresistorRpcanbereplacedbyexternalcurrentsourcepull-upstomeettherisetimerequirements.Unlessproceededbyanacknowledgebit,therisetimeoftheSCLHclockpulsesinHs-modetransfersisshortenedbytheinternalcurrent-sourcepull-upcircuitMCSoftheactivemaster.
Fig.20I2C-busconfigurationwithHs-modedevicesonly
(1)SDAandSCLarenotusedherebutmaybeusedforotherfunctions.
(2)Toinputfilter.
(3)Onlytheactivemastercanenableitscurrent-sourcepull-upcircuit
(4)Dottedtransistorsareoptionalopen-drainoutputswhichcanstretchtheserialclocksignalSCLH.
13.2SerialdatatransferformatinHs-mode
SerialdatatransferformatinHs-modemeetstheStandard-modeI2C-busspecification.Hs-modecanonlycommenceafterthefollowingconditions(allofwhichareinF/S-mode):
1.STARTcondition(S)
2.8-bitmastercode(00001XXX)
3.not-acknowledgebit(A)
Figures21and22showthisinmoredetail.Thismastercodehastwomainfunctions:
ItallowsarbitrationandsynchronizationbetweencompetingmastersatF/S-modespeeds,resultinginonewinningmaster.
ItindicatesthebeginningofanHs-modetransfer.
Hs-modemastercodesarereserved8-bitcodes,whicharenotusedforslaveaddressingorotherpurposes.Furthermore,aseachmasterhasitsownuniquemastercode,uptoeightHs-modemasterscanbepresentontheoneI2C-bussystem(althoughmastercode00001000shouldbereservedfortestanddiagnosticpurposes).
ThemastercodeforanHs-modemasterdeviceissoftwareprogrammableandischosenbytheSystemDesigner.
Arbitrationandclocksynchronizationonlytakeplaceduringthetransmissionofthemastercodeandnot-acknowledgebit(A),afterwhichonewinningmasterremainsactive.ThemastercodeindicatestootherdevicesthatanHs-modetransferistobeginandtheconnecteddevicesmustmeettheHs-modespecification.Asnodeviceisallowedtoacknowledgethemastercode,themastercodeisfollowedbyanot-acknowledge(A).
Afterthenot-acknowledgebit(A),andtheSCLHlinehasbeenpulled-uptoaHIGHlevel,theactivemasterswitchestoHs-modeandenables(attimetH,seeFig.22)thecurrent-sourcepull-upcircuitfortheSCLHsignal.AsotherdevicescandelaytheserialtransferbeforetHbystretchingtheLOWperiodoftheSCLHsignal,theactivemasterwillenableitscurrent-sourcepull-upcircuitwhenalldeviceshavereleasedtheSCLHlineandtheSCLHsignalhasreachedaHIGHlevel,thusspeedingupthelastpartoftherisetimeoftheSCLHsignal.
TheactivemasterthensendsarepeatedSTARTcondition(Sr)followedbya7-bitslaveaddress(or10-bitslaveaddress,seeSection14)withaR/Wbitaddress,andreceivesanacknowledgebit(A)fromtheselectedslave.
AfterarepeatedSTARTconditionandaftereachacknowledgebit(A)ornot-acknowledgebit(A),theactivemasterdisablesitscurrent-sourcepul
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