FPGA液晶显示和数码管显示.docx
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- 上传时间:2022-11-16
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FPGA液晶显示和数码管显示.docx
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FPGA液晶显示和数码管显示
Verilog_12864
modulelcd(clk,rs,rw,en,dat);
inputclk;
output[7:
0]dat;
outputrs,rw,en;
//trien;
rege;
reg[7:
0]dat;
regrs;
reg[15:
0]counter;
reg[5:
0]current,next;
regclkr;
reg[1:
0]cnt;
parameterset0=6'h0;
parameterset1=6'h1;
parameterset2=6'h2;
parameterset3=6'h3;
parameterset4=6'h4;
parameterset5=6'h5;
parameterset6=6'h6;
parameterdat0=6'h7;
parameterdat1=6'h8;
parameterdat2=6'h9;
parameterdat3=6'hA;
parameterdat4=6'hB;
parameterdat5=6'hC;
parameterdat6=6'hD;
parameterdat7=6'hE;
parameterdat8=6'hF;
parameterdat9=6'h10;
parameterdat10=6'h12;
parameterdat11=6'h13;
parameterdat12=6'h14;
parameterdat13=6'h15;
parameterdat14=6'h16;
parameterdat15=6'h17;
parameterdat16=6'h18;
parameterdat17=6'h19;
parameterdat18=6'h1A;
parameterdat19=6'h1B;
parameterdat20=6'h1C;
parameterdat21=6'h1D;
parameterdat22=6'h1E;
parameterdat23=6'h1F;
parameterdat24=6'h20;
parameterdat25=6'h21;
parameterdat26=6'h22;
parameterdat27=6'h23;
parameterdat28=6'h24;
parameternul=6'hF1;
always@(posedgeclk)
begin
counter=counter+1;
if(counter==16'h000f)
clkr=~clkr;
end
always@(posedgeclkr)
begin
current=next;
case(current)
set0:
beginrs<=0;dat<=8'h30;next<=set1;end//*设置8位格式,
set1:
beginrs<=0;dat<=8'h0C;next<=set2;end//*整体显示,关光标,不闪烁*/
set2:
beginrs<=0;dat<=8'h6;next<=set3;end//*设定输入方式,增量不移位*/
set3:
beginrs<=0;dat<=8'h1;next<=dat0;end//*清除显示*/
dat0:
beginrs<=1;dat<=8'hc9;next<=dat1;end//显示第一行
dat1:
beginrs<=1;dat<=8'hee;next<=dat2;end
dat2:
beginrs<=1;dat<=8'hdb;next<=dat3;end
dat3:
beginrs<=1;dat<=8'hda;next<=dat4;end
dat4:
beginrs<=1;dat<=8'hca;next<=dat5;end
dat5:
beginrs<=1;dat<=8'hd0;next<=dat6;end
dat6:
beginrs<=1;dat<="2";next<=dat7;end
dat7:
beginrs<=1;dat<="1";next<=dat8;end
dat8:
beginrs<=1;dat<="E";next<=dat9;end
dat9:
beginrs<=1;dat<="D";next<=dat10;end
dat10:
beginrs<=1;dat<=8'hB5;next<=dat11;end
dat11:
beginrs<=1;dat<=8'hE7;next<=dat12;end
dat12:
beginrs<=1;dat<=8'hd7;next<=dat13;end
dat13:
beginrs<=1;dat<=8'hd3;next<=set4;end
set4:
beginrs<=0;dat<=8'h90;next<=dat14;end//显示第二行
dat14:
beginrs<=1;dat<="N";next<=dat15;end
dat15:
beginrs<=1;dat<="I";next<=dat16;end
dat16:
beginrs<=1;dat<="O";next<=dat17;end
dat17:
beginrs<=1;dat<="S";next<=dat18;end
dat18:
beginrs<=1;dat<="";next<=set5;end
dat19:
beginrs<=1;dat<="I";next<=dat20;end
dat20:
beginrs<=1;dat<="I";next<=set5;end
set5:
beginrs<=0;dat<=8'h88;next<=dat21;end//显示第三行
dat21:
beginrs<=1;dat<="F";next<=dat22;end
dat22:
beginrs<=1;dat<="P";next<=dat23;end
dat23:
beginrs<=1;dat<="G";next<=dat24;end
dat24:
beginrs<=1;dat<="A";next<=set6;end
set6:
beginrs<=0;dat<=8'h98;next<=dat25;end//显示第四行
dat25:
beginrs<=1;dat<="S";next<=dat26;end
dat26:
beginrs<=1;dat<="O";next<=dat27;end
dat27:
beginrs<=1;dat<="P";next<=dat28;end
dat28:
beginrs<=1;dat<="C";next<=nul;end
nul:
beginrs<=0;dat<=8'h00;//把液晶的E脚拉高
if(cnt!
=2'h2)
begin
e<=0;next<=set0;cnt<=cnt+1;
end
else
beginnext<=nul;e<=1;
end
end
default:
next=set0;
endcase
end
assignen=clkr|e;
assignrw=0;
endmodule
verilog写的LCD1602显示
//LCD_Top.v
//连接Clock_Gen模块和LCD_Driver模块
moduleLCD_Top(clk_48M,rst,LCD_EN,RS,RW,DB8);
input clk_48M,rst;
output LCD_EN,RS,RW;
output [7:
0]DB8;
wire clk_LCD; //用于将Clock_Gen模块clk_LCD输出连接至LCD_Driver模块的clk_LCD输入
Clock_Gen U1(.clk_48M(clk_48M),
.rst(rst),
.clk_LCD(clk_LCD));
LCD_Driver U2(.clk_LCD(clk_LCD),
.rst(rst),
.LCD_EN(LCD_EN),
.RS(RS),
.RW(RW),
.DB8(DB8));
endmodule
//Clock_Gen.v
/****************为LCD_Drvier模块产生500Hz的时钟信号**************/
moduleClock_Gen(clk_48M,rst,clk_LCD);
input clk_48M,rst; //rst为全局复位信号(高电平有效)
output clk_LCD;
wire clk_counter;
reg [11:
0] cnt; //对时钟进行计数分频
wire clk_equ;
reg [9:
0]count;
reg clk_BUF;
parameter counter=50; //多少分频
/********************************************************************************
**模块名称:
分频器
**功能描述:
通过计数器实现分频功能.
********************************************************************************/
always@(posedgeclk_48M)
begin
if(!
rst) //低电平复位
cnt<=12'd0;
else
if(clk_equ)
cnt<=12'd0;
else
cnt<=cnt+1'b1;
end
assignclk_equ=(cnt==counter);
assignclk_counter=clk_equ;
always@(posedgeclk_counterornegedgerst)
begin //利用计数器分频产生500Hz时钟
if(!
rst)
begin
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- 关 键 词:
- FPGA 液晶显示 数码管 显示