EDA考试参考程序.docx
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EDA考试参考程序.docx
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EDA考试参考程序
第一题
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYcounterIS
GENERIC(count_value:
INTEGER:
=9);
PORT(clk,clr,en,load,dir:
INSTD_LOGIC;
data_in:
ININTEGERRANGE0TOcount_value;
ledout:
OUTSTD_LOGIC_VECTOR(6DOWNTO0));
ENDcounter;
ARCHITECTUREaOFcounterIS
SIGNALcnt:
INTEGERRANGE0TOcount_value;
SIGNALled:
STD_LOGIC_VECTOR(6DOWNTO0);
BEGIN
PROCESS(load,clk)
BEGIN
IFload='1'THEN
cnt<=data_in;
elsifclr='1'THEN
cnt<=0;
ELSIF(clk'EVENTANDclk='1')THEN
IFen='1'THEN
IFdir='1'THEN
IFcnt=count_valueTHEN
cnt<=0;
ELSE
cnt<=cnt+1;
endif;
else
IFcnt=0THEN
cnt<=count_value;
else
cnt<=cnt-1;
endif;
endif;
endif;
endif;
ENDPROCESS;
ledout<=NOTled;
WITHcntSELECT
led<="1111001"WHEN1,
"0100100"WHEN2,
"0110000"WHEN3,
"0011001"WHEN4,
"0010010"WHEN5,
"0000010"WHEN6,
"1111000"WHEN7,
"0000000"WHEN8,
"0010000"WHEN9,
"1000000"WHEN0,
"1111111"WHENothers;
ENDa;
第二题分频器
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYdiv4IS
PORT(clk:
INSTD_LOGIC;
din:
INSTD_LOGIC_VECTOR(3DOWNTO0);
fout:
OUTstd_LOGIC);
ENDdiv4;
ARCHITECTUREaOFdiv4IS
begin
process(clk)
variablecnt:
std_logic_vector(3downto0);
begin
if(clk'eventandclk='1')then
ifcnt="1111"then
cnt:
="0000";
else
cnt:
=cnt+'1';
endif;
ifdin="0000"then
fout<=cnt(3);
elsifdin="1000"then
fout<=cnt
(2);
elsifdin="1100"then
fout<=cnt
(1);
elsifdin="1110"then
fout<=cnt(0);
else
fout<='1';
endif;
endif;
endprocess;
enda;
第三题
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYdivIS
GENERIC(num:
INTEGER:
=2);
PORT
(clk:
INSTD_LOGIC;
co:
OUTSTD_LOGIC);
ENDdiv;
ARCHITECTURErtlOFdivIS
BEGIN
PROCESS(clk)
VARIABLEcnt:
STD_LOGIC_VECTOR(numdownto0);
BEGIN
IF(clk'eventandclk='1')THEN
cnt:
=cnt+'1';
ENDIF;
co<=cnt(num);
ENDPROCESS;
ENDrtl;
第四题
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYdivIS
PORT(clk:
INSTD_LOGIC;
din:
INSTD_LOGIC_VECTOR(3DOWNTO0);
COUNT:
OUTSTD_LOGIC);
ENDdiv;
ARCHITECTURErtlOFdivIS
SIGNALco:
STD_LOGIC;
BEGIN
count<=co;
PROCESS(clk)
VARIABLEcnt:
STD_LOGIC_VECTOR(3DOWNTO0);
BEGIN
IF(clk'eventandclk='1')then
if(cnt="1111")then
cnt:
="0000";
co<=notco;
elsif(cnt=din)then
co<=notco;
cnt:
=cnt+'1';
else
cnt:
=cnt+'1';
endif;
endif;
endprocess;
endrtl;
第五题
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityfenpinis
port(clk:
instd_logic;
en:
instd_logic_vector(1downto0);
cout:
outstd_logic;
ledout:
outstd_logic_vector(6downto0));
endfenpin;
architecturedgnfenpinoffenpinis
signalled:
std_logic_vector(6downto0);
signalhex:
std_logic_vector(3downto0);
begin
process(clk)
variablecnt:
std_logic_vector(3downto0);
begin
if(clk'eventANDclk='1')then
if(en="00")then
if(cnt>="1000")then
cnt:
="0000";
else
cnt:
=cnt+'1';
endif;
cout<=cnt
(2);
elsif(en="01")then
if(cnt>="1010")then
cnt:
="0000";
cout<='1';
else
cnt:
=cnt+'1';
cout<='0';
endif;
elsif(en="10")then
if(cnt>="1110")then
cnt:
="0000";cout<='1';
else
cnt:
=cnt+'1';cout<='0';
endif;
else
if(cnt>="1111")then
cnt:
="0000";
else
cnt:
=cnt+'1';
endif;
cout<=cnt(3);
endif;
endif;
endprocess;
ledout<=notled;
withenselect
led<="0000000"when"00",
"0001000"when"01",
"0001110"when"10",
"1000000"when"11",
"1111111"whenothers;
enddgnfenpin;
第六题
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYcounterIS
PORT(MA,MB:
INSTD_LOGIC;
clk:
INSTD_LOGIC;
ledout:
OUTSTD_LOGIC_VECTOR(6downto0));
ENDcounter;
ARCHITECTUREaOFcounterIS
SIGNALcnt:
STD_LOGIC_VECTOR(3downto0);
SIGNALled:
STD_LOGIC_VECTOR(6downto0);
BEGIN
PROCESS(clk)
BEGIN
IF(clk'EVENTANDclk='1')THEN
IF(MA='0'ANDMB='0')THEN
IFcnt>="0011"THEN
cnt<="0000";
ELSE
cnt<=cnt+'1';
ENDIF;
ELSIF(MA='0'ANDMB='1')THEN
IFcnt>="0101"THEN
cnt<="0000";
ELSE
cnt<=cnt+'1';
ENDIF;
ELSIF(MA='1'ANDMB='0')THEN
IFcnt>="0111"THEN
cnt<="0000";
ELSE
cnt<=cnt+'1';
ENDIF;
ELSIF(MA='1'ANDMB='1')THEN
IFcnt>="1001"THEN
cnt<="0000";
ELSE
cnt<=cnt+'1';
ENDIF;
ENDIF;
ENDIF;
ENDPROCESS;
ledout<=NOTled;
WITHcntSELECT
led<="1111001"WHEN"0001",
"0100100"WHEN"0010",
"0110000"WHEN"0011",
"0011001"WHEN"0100",
"0010010"WHEN"0101",
"0000010"WHEN"0110",
"1111000"WHEN"0111",
"0000000"WHEN"1000",
"0010000"WHEN"1001",
"1000000"WHENothers;
ENDa;
第七题
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycounteris
port(clk,clk1,en,clr:
instd_logic;
co,scanout:
outstd_logic;
ledout:
outstd_logic_vector(6downto0));
endcounter;
architecturertlofcounteris
signalcnt:
std_logic_vector(7downto0);
signalled:
std_logic_vector(6downto0);
signalscan:
std_logic;
signalhex:
std_logic_vector(3downto0);
begin
process(clk,clr)
begin
ifclr='1'then
cnt<=(others=>'0');
elsifclk'eventandclk='1'then
ifen='1'then
ifcnt="00001001"then
cnt<="00010000";
co<='0';
elsifcnt="00011001"then--注意此处,前面跳过了A到F的计数,所以计数到11001
cnt<="00000000";
co<='1';
else
cnt<=cnt+'1';
co<='0';
endif;
endif;
endif;
endprocess;
process(clk1)
begin
ifclk1'eventandclk1='1'then
scan<=notscan;
endif;
endprocess;
ledout<=notled;
scanout<=scan;
hex<=cnt(7downto4)whenscan='1'elsecnt(3downto0);
withhexselect
led<="1111001"when"0001",
"0100100"when"0010",
"0110000"when"0011",
"0011001"when"0100",
"0010010"when"0101",
"0000010"when"0110",
"1111000"when"0111",
"0000000"when"1000",
"0010000"when"1001",
"1000000"when"0000",
"1111111"whenothers;
endrtl;
第八题序列发生器
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityxulieis
port(clk:
instd_logic;
fout:
outstd_logic);
endxulie;
architecturefashengqiofxulieis
signalcnt:
std_logic_vector(2downto0);
begin
process(clk)
begin
if(clk'eventANDclk='1')then
if(cnt="111")then
cnt<="000";
else
cnt<=cnt+'1';
endif;
endif;
endprocess;
withcntselect
fout<='1'when"000",
'1'when"001",
'0'when"010",
'1'when"011",
'1'when"100",
'0'when"101",
'1'whenothers;
endfashengqi;
第九题
libraryieee;
useieee.std_logic_1164.all;
entitycaidengis
port(rl,clk:
instd_logic;
ledout:
outstd_logic_vector(15downto0));
endcaideng;
architectureaofcaidengis
signalled:
std_logic_vector(15downto0);
signalk:
std_logic;
begin
process(clk)
begin
if(clk'eventandclk='1')then
if(k='0')then
led<=(0=>'1',1=>'1',2=>'1',others=>'0');
k<='1';
elsif(rl='1')then
led<=led(14downto0)&led(15);
elsif(rl='0')then
led<=led(0)&led(15downto1);
endif;
endif;
ledout<=led;
endprocess;
enda;
第十题
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYshifter1IS
PORT(clk,clr,ser,dir,stld:
INSTD_LOGIC;
din:
INSTD_LOGIC_VECTOR(0TO7);
qh:
OUTSTD_LOGIC);
ENDshifter1;
ARCHITECTURErt1OFshifter1IS
SIGNALreg:
STD_LOGIC_VECTOR(0TO7);
begin
process(clk,clr)
begin
ifclr='1'then
reg<=(others=>'0');
elsifclk'eventandclk='1'then
ifstld='0'then
reg<=din;
else
if(dir='0')then
reg<=reg(1to7)&ser;qh<=reg(0);
else
reg<=ser®(0to6);qh<=reg(7);
endif;
endif;
endif;
endprocess;
endrt1;
第十一题
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityselectoris
port(b:
instd_logic_vector(6downto0);
clr:
instd_logic;
red,gree:
outstd_logic;
ledout:
outstd_logic_vector(6downto0));
endselector;
architecturertlofselectoris
signalled:
std_logic_vector(6downto0);
signalcount:
std_logic_vector(3downto0);
signala:
std_logic_vector(6downto0);
begin
process(b,clr)
begin
if(clr='1')then
a<=(others=>'0');
else
foriin0to6loop
a(i)<=b(i);
endloop;
endif;
endprocess;
process(a)
variablecnt:
std_logic_vector(3downto0);
begin
cnt:
="0000";
foriin0to6loop
ifa(i)='1'then
cnt:
=cnt+'1';
endif;
endloop;
if(cnt>="0100"andcnt<="0111")then
gree<='1';
red<='0';
elsif(cnt>="0000"andcnt<"0100")then
gree<='0';
red<='1';
endif;
count<=cnt;
endprocess;
ledout<=notled;
withcountselect
led<="1111001"when"0001",
"0100100"when"0010",
"0110000"when"0011",
"0011001"when"0100",
"0010010"when"0101",
"0000010"when"0110",
"1000000"whenothers;
endrtl;
第十二题
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYshifterIS
PORT(clk,clr,ser,stld:
INSTD_LOGIC;
din:
INSTD_LOGIC_VECTOR(0TO7);
qh:
OUTSTD_LOGIC);
ENDshifter;
ARCHITECTURErt1OFshifterIS
SIGNALreg:
STD_LOGIC_VECTOR(0TO7);
begin
process(clk,clr)
begin
ifclr='1'then
reg<=(others=>'0');
elsifclk'eventandclk='1'then
ifstld='0'then
reg<=din;
else
reg<=reg(1to7)&ser;
endif;
endif;
endprocess;
qh<=reg(0);
endrt1;
第十三题
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYbhxsIS
PORT(INPUT:
INSTD_LOGIC_VECTOR(15DOWNTO0);
LEDOUT:
outSTD_LOGIC_VECTOR(6DOWNTO0));
ENDbhxs;
ARCHITECTURERT1OFbhxsIS
SIGNALLED:
STD_LOGIC_VECTOR(6DOWNTO0);
BEGIN
process(INPUT)
begin
LEDOUT<=NOTLED;
IF(INPUT(0)='1')then
LED<="1000000";
ELSIF(INPUT
(1)='1')then
LED<="1111001";
ELSIF(INPUT
(2)='1')then
LED<="0100100";
ELSIF(INPUT(3)='1')then
LED<="0110000";
ELSIF(INPUT(4)='1')then
LED<="0011001";
ELSIF(INPUT(5)='1')then
LED<="0010010";
ELSIF(INPUT(6)='1')then
LED<="0000010";
ELSIF(INPUT(7)='1')then
LED<="1111000";
ELSIF(INPUT(8)='1')then
LED<="0000000";
ELSIF(INPUT(9)='1')then
LED<="0010000";
ELSIF(INPUT(10)=
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