英文翻译存储器子系统的组成与接口.docx
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英文翻译存储器子系统的组成与接口.docx
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英文翻译存储器子系统的组成与接口
附录10:
英文原文
MemorySubsystemOrganizationandInterfacing
Inthissectionweexaminetheconstructionandfunctionsofthememorysubsystemofacomputer.Wereviewthedifferenttypesofphysicalmemoryandtheinternalorganizationoftheirchips.Wediscusstheconstructionofthememorysubsystem,aswellasmultibytewordorganizationsandadvancedmemoryorganizations.
1TypesofMemory
Therearetwotypesofmemorychips;readonlymemory(ROM)andrandomaccessmemory(RAM).ReadOnlyMemory(ROM)chipsaredesignedforapplicationsinwhichdataisonlyread.(Thisdatacanincludeprograminstructions.)Thesechipsareprogrammedwithdatabyanexternalprogrammingunitbeforetheyareaddedtothecomputersystem.Oncethisisdone,thedatausuallydoesnotchange.AROMchipalwaysretainsitsdata,evenwhenpowertothechipisturnedoff.Asanexample,anembeddedcontrollerforamicrowaveovenmightcontinuouslyrunoneprogramthatdoesnotchange.ThatprogramwouldbestoredinaROM.
RandomAccessMemory(RAM),alsocalledread/writememory,canbeusedtostoredatathatchange.ThisisthetypeofmemoryreferredtoasXMBofmemoryinadsforPCs.UnlikeROM,RAMchipslosetheirdataoncepowerisshutoff.Manycomputersystem,includingpersonalcomputers,includebothROMandRAM.
2InternalChipOrganization
TheinternalorganizationsofROMandRAMchipsaresimilar.Toillustratethesimplestorganization,alinearorganization,consideran8x2ROMchip.Forsimplicity,programmingcomponentsarenotshown。
Thischiphasthreeaddressinputsandtwodataoutputs,and16bitsofinternalstoragearrangedaseight2-bitlocations.
Thethreeaddressbitsaredecodedtoselectoneoftheeightlocations,butonlyifthechipenableisactive.IfCE=0,thedecoderiddisabledandnolocationisselected.Thetri-statebuffersforthatlocation‘scellsareenabled,allowingdatatopasstotheoutputbuffers.IfbothCEandOEsetto1,thesebuffersareenabledandthedataisoutputfromthechip;otherwisetheoutputsaretri-stated.
Asthenumberofthelocationsincreases,thesizeoftheaddressdecoderneededinalinearorganizationbecomesprohibitivelylarge.Toremedythisproblem,thememorychipcanbedesignedusingmultipledimensionsofdecoding.
Inlargememorychips,thissavingscanbesignificant.Considera4096x1chip.Thelinearorganizationwillrequirea12to4096decoder,thesizeofwhichisproportionaltothenumberofoutputs.(Thesizeofannto
decoderidthussaidtobeO(
).)Ifthechipisorganizedasa64x64twodimensionalarrayinstead,itwillhavetwo6to64decoders:
onetoselectoneofthe64rowsandtheothertoselectoneofthe64cellswithintherow.Thesizeofthedecodersisproportionalto2x64,orO(2x
)=O(
).Forthischip,thetwodecoderstogetherareabout3percentofthesizeoftheonelargedecoder.
3MemorySubsystemConfiguration
Itisveryeasytosetupamemorysystemthatconsistsofasinglechip.Wesimpleyconnecttheaddress,data,andcontrolsignalsfromtheirsystembusesandthejobisdone.However,mostmemorysystemsrequiremorethanonechip.Followingaresomemethodsforcombiningmemorychipstoformamemorysubsystem.
Twoormorechipscanbecombinedtocreatememorywithmorebitsperlocation.Thisisdonebyconnectingthecorrespondingaddressandcontrolsignalsofthechips,andconnectingtheirdatapinstodifferentbitsofthedatabus.Forexample,two8x2chipscanbecombinedtocreatean8x4memory,asshowninFigure2-4.Bothchipsreceivethesamethreeaddressinputsfromthebus,aswellasthesamechipenableandoutputenablesignals.(Fornowitisonlyimportanttoknowthatthesignalsarethesameforbothchips;weshowthelogictogeneratethesesignalsshortly.)Thedatapinsofthefirstchipareconnectedtobits3and2ofthedatabus,andthoseoftheotherchipareconnectedtobits1and0.
Figure4An8x4memorysubsystemconstructedfromtwo8x2ROMChips
WhentheCPUreadsdata,itplacestheaddressontheaddressbus.BothchipsreadinaddressbitsA2,A1,andAoandperfonntheirintemaldecoding.IftheCEandOEsignalsareactivated,thechipsoutputtheirdataontothefombitsofthedatabus.Sincetheaddressandenablesignalsarethesameforbothchips,eitherbothchipsorneitherchipisactiveatanygiventime.Thecomputerneverhasonlyoneofthetwoactive.Forthisreason,theyactjustasasingle8x4chip,atleastasfarastheCPUisconcerned.
Insteadofcreatingwiderwords,chipscanbecombinedtocreatemorewords.Thesametwo8x2chipscouldinsteadbeconfiguredasa16x2memorysubsystem.ThisisillustratedinFigure2-5(a).Theupperchipisconfiguredas'memorylocations0to7(0000toOIII)andthelowerchipaslocations8to15(IOOOtollIl).TheupperchipalwayshasA3=0andthelowerchiphasA3=I.Thisdifferenceisusedtoselectoneofthetwochips.WhenA3=0,theupperchipisenabledandthelowerchipisdisabled;whenA3=1,theoppositeoccurs.(Asshowninthefigure9otherconditionsmustalsooccurorneitherchipwillbeselected.)Theoutputenablescanbeconnected,sinceonlythechipthatisenabledwilloutputdata.Sincebothchipscorrespondtothesamedatabits,bothareconnectedtoDIandDoofthedatabus.
Thisconfigurationuseshigh-orderinterleaving.Allmemorylocationswithinachiparecontiguouswithinsystemmemory.However,thisdoesnothavetobethecase.ConsidertheconfigurationshowninFigure2-5(b),whichuseslow-orderinterleaving.TheupperchipisenabledwhenA0=0orbyaddressesXXX0,inthiscase0,2,4,6,8,10,12,and14.Thelowerchipisenabledwhen.A0=1,whichistrueforaddresses1,3,5,7,9,11,13and15.BothlookthesametotheCPU,butlow-orderinterleavingcanoffersomespeedadvantagesforpipelinedmemoryaccess,andforCPUsthatcanreaddatafrommorethanonememorylocationsimultaneously.
(a)high-orderinterleaving(b)low-orderinterleaving
Figure5A16x2memorysubsystemconstructedfromtwo8x2ROMChips
ThenextstepinthesedesignsistodeveloptheCEorOEinputlogic.Ofthese,theoutputenableismorestraightforward.TheCPUgenerallyoutputsacontrolsignalcalledRDorRD’,orsomethingsimilar,whichitsetsactivewhenitwantstoreaddatafrommemory.ThissignalissufficienttodriveOE;thelogictodriveCEensuresthatonlythecorrectchipoutputdata.
Thechipenablesignalmakesuseoftheunusedaddressbits.Toillustrate,assumethatthe8x4memoryofFigure2-4isusedinasystemwith6-bitaddressbus.Furthermore,assumethischipcorrespondstolocations0to7(000000to000111).AddressbitsA2,A1,andA0selectalocationwithinthememorychips;bitsA5,A4,andA3mustbe000forthechipstobeactive.
4MultibyteDataOrganization
Manydataformatusemorethanone8-bitbytetorepresentavalue,whetheritisaninteger,floatingpointnumber,orcharacterstring.MostCPUsassignaddressesto8-bitmemorylocations,sothesevaluesmustbestoredinmorethanonelocation.ItisnecessaryforeveryCPUtodefinetheorderitexpectsforthedataintheselocations.
Thesearetwocommonlyusedorganizationsformultibytedata:
bigendianandlittleendian.Inbigendainformat,themostsignificantbyteofavalueisstoredinlocationX,thefollowingbyteinlocationX+1,andsoon.Forexample,thehexadecimalvalue01020304H(Hforhexadecimal)wouldbestored,startinginlocation100H,asshowninTable1(a).
Inlittleendian,theorderisreversed.TheleastsignificantbyteisstoredinlocationX,thenextbyteinlocationX+1,andsoon.Thesamevalue,inlittleendianformat,isshowninTable1(a).
MemoryAddress
Data(inhex)
100
101
102
103
04
03
02
01
(a)bigendianformats
MemoryAddress
Data(inhex)
100
101
102
103
01
02
03
04
(b)littleendianformats
Thesameorganizationscanbeusedforbitswithinabyte.Inbigendianorganization,bit0istherightmostbitofabyte:
theleftmostbitisbit7.Inlittleendianorganization,theleftmostbitisbit0andbit7istherightmostbit.Table1Dataorganizationinbigandlittleendianformats.
WhichendianorganizationisusedforbytesandwordsdoesnotimpacttheperformanceoftheCPUandcomputersystem.AslongastheCPUisdesignedtohandleaspecificformat,neverisbetterthantheother.Themainproblemcomesintransferringdatabetweencomputerswithdifferentendianorganizations.Forexample,ifacomputerwithinlittleendianorganizationstransferthevalue01020304Htoacomputerwithbigendianorganizationwithoutconvertingthedata,thebigendiancomputerwillreadthevalueas04030201HThereareprogramswhichcanconvertdatafilesfromoneformattotheother,andsomemicroprocessorshavespecialinstructionstoperformtheconversion.
0neotherissueofconcernformultibytewordsisalignment.Modernmicroprocessorscanreadinmorethanonebyteofdataatatime.Forexample,theMotorola68040microprocessorcanreadinfourbytessimultaneously.Howeverthefourbytesmustbeinconsecutivelocationsthathavethesameaddressexpectforthetwoleastsignificantbits.ThisCPUcouldreadlocations100,101,102,andl03simultaneously.butnotlocationsl01,102,103,andl04.Thiscasewouldrequiretworeadoperations,oneforlocations100(notneeded),101,102,andl03,andtheotherfor104,105(notneeded),106(notneeded),andl07(notneeded).
Alignmentsimplymeansstoringmu1tibytevaluesinlocationssuchthattheybeginata1ocationthatalsobeginsamultibytereadblock.Inthisexample,thismeansbeginningmultibytevaluesatmemorylocationsthathaveaddressesevenlydivisiblebyfour,thusgua
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