万年历quartus仿真.docx

万年历quartus仿真.docx

《万年历quartus仿真.docx》由会员分享，可在线阅读，更多相关《万年历quartus仿真.docx（23页珍藏版）》请在冰豆网上搜索。

万年历quartus仿真

秒模块（60进制计数器）

libraryieee;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYmiaoIS

PORT（chu,CLK:

INSTD_LOGIC;

CQ1,CQ2:

OUTSTD_LOGIC_VECTOR（3DOWNTO0）;

COUT:

OUTSTD_LOGIC）;

ENDmiao;

ARCHITECTUREbehavOFmiaoIS

signalQ1,Q2:

STD_LOGIC_VECTOR（3DOWNTO0）;

BEGIN

PROCESS（chu,CLK）

BEGIN

ifchu='1'then

Q1<="0000";Q2<="0000";

ELSIFCLK'EVENTANDCLK='1'THEN

Q1<=Q1+1;

IFQ1=9THENQ1<="0000";Q2<=Q2+1;

ENDIF;

IFQ2=5ANDQ1=9THEN

Q1<="0000";Q2<="0000";COUT<='1';

ELSECOUT<='0';

ENDIF;

ENDIF;

CQ1<=Q1;CQ2<=Q2;

ENDPROCESS;

END;

分模块（60进制计数器）

libraryieee;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYfenIS

PORT（chu,CLK:

INSTD_LOGIC;

S1,S2:

INSTD_LOGIC_VECTOR（3DOWNTO0）;

CQ1,CQ2:

OUTSTD_LOGIC_VECTOR（3DOWNTO0）;

COUT:

OUTSTD_LOGIC）;

ENDfen;

ARCHITECTUREbehavOFfenIS

signalQ1,Q2:

STD_LOGIC_VECTOR（3DOWNTO0）;

BEGIN

PROCESS（chu,CLK）

BEGIN

ifchu='1'then

Q1<=S1;Q2<=S2;

ELSIFCLK'EVENTANDCLK='1'THEN

Q1<=Q1+1;

IFQ1=9THENQ1<="0000";Q2<=Q2+1;

ENDIF;

IFQ2=5ANDQ1=9THEN

Q1<="0000";Q2<="0000";COUT<='1';

ELSECOUT<='0';

ENDIF;

ENDIF;

CQ1<=Q1;CQ2<=Q2;

ENDPROCESS;

END;

时模块（24进制计数器）

libraryieee;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYshiIS

PORT（chu,CLK:

INSTD_LOGIC;

S1,S2:

INSTD_LOGIC_VECTOR（3DOWNTO0）;

CQ1,CQ2:

OUTSTD_LOGIC_VECTOR（3DOWNTO0）;

COUT:

OUTSTD_LOGIC）;

ENDshi;

ARCHITECTUREbehavOFshiIS

signalQ1,Q2:

STD_LOGIC_VECTOR（3DOWNTO0）;

BEGIN

PROCESS（chu,CLK）

BEGIN

ifchu='1'then

Q1<=S1;Q2<=S2;

ELSIFCLK'EVENTANDCLK='1'THEN

Q1<=Q1+1;

IFQ1=9THENQ1<="0000";Q2<=Q2+1;

ENDIF;

IFQ2=2ANDQ1=3THEN

Q1<="0000";Q2<="0000";COUT<='1';

ELSECOUT<='0';

ENDIF;

ENDIF;

CQ1<=Q1;CQ2<=Q2;

ENDPROCESS;

END;

日模块（31进制计数器）

Entityriis

Port（chu,clk:

instd_logic;

a,b:

instd_logic;

S1,S2:

INSTD_LOGIC_VECTOR（3DOWNTO0）;

T1,T2:

outstd_logic_vector（3downto0）;

cout:

outstd_logic）;

endri;

Architectureoneofriis

signalQ1,Q2:

STD_LOGIC_VECTOR（3DOWNTO0）;

signalab:

STD_LOGIC_VECTOR（1DOWNTO0）;

Begin

PROCESS（chu,clk,a,b）

begin

ifchu='1'thenQ1<=S1;Q2<=S2;

ELSIFCLK'EVENTANDCLK='1'THEN

Q1<=Q1+1;

IFQ1=9THENQ1<="0000";Q2<=Q2+1;

endif;

ab<=a&b;

caseabis

when"00"=>ifQ2=3ANDQ1=1THENQ2<="0000";Q1<="0001";cout<='1';elsecout<='0';

endif;

when"01"=>

ifQ2=3andQ1=0THEN

Q2<="0000";Q1<="0001";cout<='1';

elsecout<='0';

endif;

when"10"=>

ifQ2=2ANDQ1=8then

Q2<="0000";Q1<="0001";cout<='1';

elsecout<='0';

endif;

when"11"=>

ifQ2=2ANDQ1=9then

Q2<="0000";Q1<="0001";cout<='1';

elsecout<='0';

endif;

whenothers=>NULL;

endcase;

ENDIF;

T1<=Q1;

T2<=Q2;

ENDPROCESS;

ENDARCHITECTUREone;

月模块（12进制计数器）

libraryieee;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYyueIS

PORT（chu,CLK,run:

INSTD_LOGIC;

S1,S2:

INSTD_LOGIC_VECTOR（3DOWNTO0）;

Y1,Y2:

OUTSTD_LOGIC_VECTOR（3DOWNTO0）;

a,b:

OUTSTD_LOGIC;

COUT:

OUTSTD_LOGIC）;

ENDyue;

ARCHITECTUREONEOFyueIS

signalQ2,Q1:

STD_LOGIC_VECTOR（3DOWNTO0）;

signalQ2Q1:

STD_LOGIC_VECTOR（7DOWNTO0）;

BEGIN

PROCESS（chu,CLK,run）

BEGIN

IFchu='1'then

Q1<=S1;Q2<=S2;

elsIFCLK'EVENTANDCLK='1'THEN

Q1<=Q1+1;

IFQ1=9THENQ1<="0000";Q2<=Q2+1;

ENDIF;

IFQ2=1ANDQ1=2THENQ1<="0001";Q2<="0000";COUT<='1';

ELSECOUT<='0';

ENDIF;

endif;

endPROCESS;

PROCESS（q2,q1）

begin

Q2Q1<=Q2&Q1;

caseQ2Q1is

when"00000001"=>a<='0';b<='0';

when"00000010"=>ifrun='1'thena<='1';b<='1';elsea<='1';b<='0';endif;

when"00000011"=>a<='0';b<='0';

when"00000100"=>a<='0';b<='1';

when"00000101"=>a<='0';b<='0';

when"00000110"=>a<='0';b<='1';

when"00000111"=>a<='0';b<='0';

when"00001000"=>a<='0';b<='0';

when"00001001"=>a<='0';b<='1';

when"00010000"=>a<='0';b<='0';

when"00010001"=>a<='0';b<='1';

when"00010010"=>a<='0';b<='0';

whenothers=>null;

endcase;

ENDPROCESS;

Y1<=Q1;Y2<=Q2;

ENDARCHITECTUREONE;

年模块（一万进制计数器）

libraryieee;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYnianIS

PORT（chu,A,B,CLK:

INSTD_LOGIC;

S1,S2:

INSTD_LOGIC_VECTOR（3DOWNTO0）;

N1,N2,N3,N4:

OUTSTD_LOGIC_VECTOR（3DOWNTO0））;

ENDnian;

ARCHITECTUREABCOFnianIS

signalQ1,Q2,Q3,Q4:

STD_LOGIC_VECTOR（3DOWNTO0）;

signalZ:

STD_LOGIC_VECTOR（1DOWNTO0）;

BEGIN

PROCESS（chu,A）

BEGIN

IFchu='1'then

CASEAIS

WHEN'1'=>

Q4<=S2;Q3<=S1;

when'0'=>

Q2<=S2;Q1<=S1;

WHENOTHERS=>NULL;

ENDCASE;

--IFA='0'THENQ4<="0010";Q3<="0000";Q2<="0001";Q1<="0001";

--ELSIFB='1'THENQ4<=S2;Q3<=S1;

--ELSEQ2<=S2;Q1<=S1;

--ENDIF;

--ENDIF;

ELSIFCLK'EVENTANDCLK='1'THEN

Q1<=Q1+1;

IFQ1=9THENQ1<="0000";Q2<=Q2+1;

ENDIF;

IFQ2=9aANDQ1=9THENQ2<="0000";Q3<=Q3+1;

ENDIF;

IFQ3=9ANDQ2=9andQ1=9THENQ3<="0000";Q4<=Q4+1;

ENDIF;

IFQ4=9ANDQ3=9ANDQ2=9ANDQ1=9THEN

Q1<="0000";Q2<="0000";Q3<="0000";Q4<="0000";

ENDIF;

endif;

endPROCESS;

N1<=Q1;N2<=Q2;N3<=Q3;N4<=Q4;

endABC;

闰年模块

ENTITYrunnianis

PORT（n1,n2,n3,n0:

instd_logic_vector（3downto0）;

ru1:

OUTstd_logic）;

ENDrunnian;

--*********************************************

ARCHITECTUREabcOFrunnianIS

signalru:

std_logic;

BEGIN

process（n1,n2,n3,n0）

BEGIN

ifn0=0andn1=0then

ifn3（0）='0'then

ifN2=0ORN2=4ORN2=8thenru<='1';

elseru<='0';

endif;

else

ifn2=2orn2=6thenru<='1';

elseru<='0';

endif;

endif;

else

ifn1（0）='0'then

ifN0=0ORN0=4ORN0=8thenru<='1';

elseru<='0';

endif;

else

ifn0=2orn0=6thenru<='1';

elseru<='0';

endif;

endif;

endif;

ru1<=ru;

endprocess;

endabc;

星期模块（8进制计数器）

ENTITYxingqiIS

PORT（chu,CLK:

INSTD_LOGIC;

s1:

inSTD_LOGIC_VECTOR（3DOWNTO0）;

C1:

OUTSTD_LOGIC_VECTOR（3DOWNTO0））;

ENDxingqi;

ARCHITECTUREabcOFxingqiIS

signalQ1:

STD_LOGIC_VECTOR（3DOWNTO0）;

BEGIN

PROCESS（chu,CLK）

BEGIN

ifchu='1'then

Q1<=s1;

ELSIFCLK'EVENTANDCLK='1'THEN

Q1<=Q1+1;

IFQ1=7THENQ1<="0001";

ENDIF;

ENDIF;

C1<=Q1;

ENDPROCESS;

ENDabc;

生日模块

ENTITYshengriIS

Port（chu:

instd_logic;

a,b,c:

INSTD_LOGIC;

y2,y1,r2,r1:

INSTD_LOGIC_VECTOR（3DOWNTO0）;

q2,q1:

INSTD_LOGIC_VECTOR（3DOWNTO0）;

nao:

OUTSTD_LOGIC）;

ENDshengri;

ARCHITECTUREabcOFshengriIS

signaly2y1,r2r1,q2q1,sy1,sy2,sy3,sr1,sr2,sr3:

STD_LOGIC_VECTOR（7DOWNTO0）;

signalsr,s1,s2,s3:

STD_LOGIC_VECTOR（15DOWNTO0）;

signalab:

STD_LOGIC_VECTOR（1DOWNTO0）;

--signalQ2Q1:

STD_LOGIC;

BEGIN

PRocESS（a,b,c,chu）

begin

ab<=a&b;y2y1<=y2&y1;

r2r1<=r2&r1;q2q1<=q2&q1;

s1<=sy1&sr1;s2<=sy2&sr2;s3<=sy3&sr3;

sr<=y2y1&r2r1;

IFchu='1'THENifc='1'then

caseabiswhen"00"=>s1<=s1;s2<=s2;s3<=s3;

when"01"=>sy1<=q2q1;

when"10"=>sy2<=q2q1;

when"11"=>sy3<=q2q1;

whenothers=>null;

endcase;

else

caseabis

when"00"=>s1<=s1;s2<=s2;s3<=s3;

when"01"=>sr1<=q2q1;

when"10"=>sr2<=q2q1;

when"11"=>sr3<=q2q1;

whenothers=>null;

endcase;endif;endif;

ifsr=s1orsr=s2orsr=s3thennao<='1';

ELSEnao<='0';

endif;

endprocess;

endabc;

控制模块

libraryieee;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYkongIS

PORT（a,b,c,d,e,CHU,G,F:

INSTD_LOGIC;

Q1,Q2:

INSTD_LOGIC_VECTOR（3DOWNTO0）;

N1,N2,Y1,Y2,R1,R2,S1,S2,F1,F2,X1,SR1,SR2:

OUTSTD_LOGIC_VECTOR（3DOWNTO0）;

NC,NA,NB,SRC,SA,SRB,YC,RC,SC,FC,MC,XC:

OUTSTD_LOGIC）;

ENDkong;

ARCHITECTUREONEOFkongIS

signalabcde:

STD_LOGIC_VECTOR（4DOWNTO0）;

BEGIN

PROCESS（a,b,c,d,e）

BEGIN

abcde<=a&b&c&d&e;

caseabcdeis

WHEN"10000"=>N1<="0000";N2<="0010";Y1<="0001";Y2<="0000";R1<="0001";R2<="0000";S1<="1001";S2<="0000";F1<="0000";F2<="0000";X1<="0001";

NC<='1';YC<='1';RC<='1';SC<='1';FC<='1';MC<='1';XC<='1';SRC<='0';

WHEN"10001"=>N1<="0000";N2<="0010";Y1<="0001";Y2<="0000";R1<="0001";R2<="0000";S1<="1001";S2<="0000";F1<="0000";F2<="0000";X1<="0001";

NC<='1';YC<='1';RC<='1';SC<='1';FC<='1';MC<='1';XC<='1';SRC<='0';

WHEN"10010"=>N1<="0000";N2<="0010";Y1<="0001";Y2<="0000";R1<="0001";R2<="0000";S1<="1001";S2<="0000";F1<="0000";F2<="0000";X1<="0001";

NC<='1';YC<='1';RC<='1';SC<='1';FC<='1';MC<='1';XC<='1';SRC<='0';

WHEN"10011"=>N1<="0000";N2<="0010";Y1<="0001";Y2<="0000";R1<="0001";R2<="0000";S1<="1001";S2<="0000";F1<="0000";F2<="0000";X1<="0001";

NC<='1';YC<='1';RC<='1';SC<='1';FC<='1';MC<='1';XC<='1';SRC<='0';

WHEN"10100"=>N1<="0000";N2<="0010";Y1<="0001";Y2<="0000";R1<="0001";R2<="0000";S1<="1001";S2<="0000";F1<="0000";F2<="0000";X1<="0001";

NC<='1';YC<='1';RC<='1';SC<='1';FC<='1';MC<='1';XC<='1';SRC<='0';

WHEN"10101"=>N1<="0000";N2<="0010";Y1<="0001";Y2<="0000";R1<="0001";R2<="0000";S1<="1001";S2<="0000";F1<="0000";F2<="0000";X1<="0001";

NC<='1';YC<='1';RC<='1';SC<='1';FC<='1';MC<='1';XC<='1';SRC<='0';

WHEN"10110"=>N1<="0000";N2<="0010";Y1<="0001";Y2<="0000";R1<="0001";R2<="0000";S1<="1001";S2<="0000";F1<="0000";F2<="0000";X1<="0001";

NC<='1';YC<='1';RC<='1';SC<='1';FC<='1';MC<='1';XC<='1';SRC<='0';

WHEN"10111"=>N1<="0000";N2<="0010";Y1<="0001";Y2<="0000";R1<="0001";R2<="0000";S1<="1001";S2<="0000";F1<="0000";F2<="0000";X1<="0001";

NC<='1';YC<='1';RC<='1';SC<='1';FC<='1';MC<='1';XC<='1';SRC<='0';

WHEN"11000"=>N1<="0000";N2<="0010";Y1<="0001";Y2<="0000";R1<="0001";R2<="0000";S1<="1001";S2<="0000";F1<="0000";F2<="0000";X1<="0001";

NC<='1';YC<='1';RC<='1';SC<='1';FC<='1';MC<='1';XC<='1';SRC<='0';

WHEN"11001"=>N1<="0000";N2<="0010";Y1<="0001";Y2<="0000";R1<="0001";R2<="0000";S1<="1001";S2<="0000";F1<="0000";F2<="0000";X1<="0001";

NC<='1';YC<='1';RC<='1';SC<='1';FC<='1';MC<='1';XC<='1';SRC<='0';

WHEN"11010"=>N1<="0000";N2<="0010";Y1<="0001";Y2<="0000";R1<="0001";R2<="0000";S1<="1001";S2<="0000";F1<="0000";F2<="0000";X1<="0001";

NC<='1';YC<='1';RC<='1';SC<='1';FC<='1';MC<='1';XC<='1';SRC<='0';

WHEN"11011"=>N1<="0000";N2<="0010";Y1<="0001";Y2<="0000";R1<="0001";R2<="0000";S1<="1001";S2<