78910作业.docx
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78910作业.docx
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78910作业
第七章作业
7—5.将例7—4的顶层程序和例7—3的ROM程序合并成为一个程序,要求用例化语句直接调用LPM模块altsyncram,编译验证,使之功能与原设计相同。
解:
两个模块的VHDL语言:
模块一:
libraryieee;
useieee.std_logic_1164.all;
libraryaltera_mf;
usealtera_mf.altera_mf_components.all;
entitydata_romis
port(address:
instd_logic_vector(5downto0);
inclock:
instd_logic;
q:
outstd_logic_vector(7downto0));
enddata_rom;
architecturesynofdata_romis
signalsub_wire0:
std_logic_vector(7downto0);
componentaltsyncram
generic(
intended_device_family:
string;
width_a:
natural;widthad_a:
natural;
numwords_a:
natural;operation_mode:
string;
outdata_reg_a:
string;address_aclr_a:
string;
outdata_aclr_a:
string;width_byteena_a:
natural;
int_file:
string;lpm_hint:
string;
lpm_type:
string);
port(clock0:
instd_logic;
address_a:
instd_logic_vector(5downto0);
q_a:
outstd_logic_vector(7downto0));
endcomponent;
begin
q<=sub_wire0(7downto0);
altsyncram_component:
altsyncram
genericmap(intended_device_family=>"Cyclone",
width_a=>8,
widthad_a=>6,
numwords_a=>64,
operation_mode=>"ROM",
outdata_reg_a=>"unregistered",
address_aclr_a=>"none",
outdata_aclr_a=>"none",
width_byteena_a=>1,
init_file=>"./dataHEX/SDATA.hex",
lpm_hint=>"enable_runtime_mod=yes,instance_name=none",
lpm_type=>"altsyncram")
portmap(clock0=>inclock,address_a=>address,q_a=>sub_wire0);
end;
模块二:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitysingtis
port(clk:
instd_logic;
dout:
outstd_logic_vector(7downto0));
end;
architecturedaccofsingtis
componentdata_rom
port(address:
instd_logic_vector(5downto0);
inclock:
instd_logic;
q:
outstd_logic_vector(7downto0));
endcomponent;
signalQ1:
std_logic_vector(5downto0);
begin
process(clk)
begin
ifclk'eventandclk='1'thenQ1<=Q1+1;
endif;
endprocess;
u1:
data_romportmap(address=>Q1,q=>dout,inclock=>clk);
end;
对应的RTL文件:
图1RTL文件
正弦波信号发生器仿真结果:
图2正弦波信号发生器仿真结果
实验与设计
7—2.
(1)设计一个8位16进制频率计。
经分析可知,该频率计可分为一个测频率控制信号发生器,一个32位锁存器
(1)测频率控制信号发生器,产生测量频率的控制时序。
其VHDL文件:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYFTCTRLIS
PORT(CLKK:
INSTD_LOGIC;
CNT_EN:
OUTSTD_LOGIC;
RST_CNT:
OUTSTD_LOGIC;
Load:
OUTSTD_LOGIC);
ENDFTCTRL;
ARCHITECTUREbehavOFFTCTRLIS
SIGNALDiv2CLK:
STD_LOGIC;
BEGIN
PROCESS(CLKK)
BEGIN
IFCLKK'EVENTANDCLKK='1'THEN
Div2CLK<=NOTDiv2CLK;
ENDIF;
ENDPROCESS;
PROCESS(CLKK,Div2CLK)
BEGIN
IFCLKK='0'ANDDiv2CLK='0'THENRST_CNT<='1';
ELSERST_CNT<='0';ENDIF;
ENDPROCESS;
Load<=NOTDiv2CLK;CNT_EN<=Div2CLK;
ENDbehav;
编译结果,其RTL文件如图:
图3测频率控制信号发生器RTL文件
仿真结果:
图4测频率控制信号发生器仿真结果
(2)32位锁存器
其VHDL程序如下:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYREG32BIS
PORT(LK:
INSTD_LOGIC;
DIN:
INSTD_LOGIC_VECTOR(31DOWNTO0);
DOUT:
OUTSTD_LOGIC_VECTOR(31DOWNTO0));
ENDREG32B;
ARCHITECTUREbehavOFREG32BIS
BEGIN
PROCESS(LK,DIN)
BEGIN
IFLK'EVENTANDLK='1'THENDOUT<=DIN;
ENDIF;
ENDPROCESS;
ENDbehav;
运行结果的RTL文件如图:
图532位锁存器RTL文件
仿真结果:
图632位锁存器仿真结果
(3)计数器
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYCOUNTER32BIS
PORT(FIN:
INSTD_LOGIC;
CLR:
INSTD_LOGIC;
ENABL:
INSTD_LOGIC;
DOUT:
OUTSTD_LOGIC_VECTOR(31DOWNTO0));
ENDCOUNTER32B;
ARCHITECTUREbehavOFCOUNTER32BIS
SIGNALCQI:
STD_LOGIC_VECTOR(31DOWNTO0);
BEGIN
PROCESS(FIN,CLR,ENABL)
BEGIN
IFCLR='1'THENCQI<=(OTHERS=>'0');
ELSIFFIN'EVENTANDFIN='1'THEN
IFENABL='1'THENCQI<=CQI+1;ENDIF;
ENDIF;
ENDPROCESS;
DOUT<=CQI;
ENDbehav;
编译结果,其RTL文件如图:
图7计数器的RTL文件
仿真结果:
图8计数器的仿真结果
根据
(1)、
(2)、(3),综合所得8位十六进制频率计:
其VHDL文件:
LIBRARYieee;
USEieee.std_logic_1164.all;
LIBRARYwork;
ENTITYpinlvji_8IS
PORT
(
CLK:
INSTD_LOGIC;
FIN:
INSTD_LOGIC;
DOUT:
OUTSTD_LOGIC_VECTOR(31DOWNTO0)
);
ENDpinlvji_8;
ARCHITECTUREbdf_typeOFpinlvji_8IS
COMPONENTcounter32b
PORT(FIN:
INSTD_LOGIC;
CLR:
INSTD_LOGIC;
ENABL:
INSTD_LOGIC;
DOUT:
OUTSTD_LOGIC_VECTOR(31DOWNTO0)
);
ENDCOMPONENT;
COMPONENTftctrl
PORT(CLKK:
INSTD_LOGIC;
CNT_EN:
OUTSTD_LOGIC;
RST_CNT:
OUTSTD_LOGIC;
Load:
OUTSTD_LOGIC
);
ENDCOMPONENT;
COMPONENTreg32b
PORT(LK:
INSTD_LOGIC;
DIN:
INSTD_LOGIC_VECTOR(31DOWNTO0);
DOUT:
OUTSTD_LOGIC_VECTOR(31DOWNTO0)
);
ENDCOMPONENT;
SIGNALSYNTHESIZED_WIRE_0:
STD_LOGIC;
SIGNALSYNTHESIZED_WIRE_1:
STD_LOGIC;
SIGNALSYNTHESIZED_WIRE_2:
STD_LOGIC;
SIGNALSYNTHESIZED_WIRE_3:
STD_LOGIC_VECTOR(31DOWNTO0);
BEGIN
b2v_inst:
counter32b
PORTMAP(FIN=>FIN,
CLR=>SYNTHESIZED_WIRE_0,
ENABL=>SYNTHESIZED_WIRE_1,
DOUT=>SYNTHESIZED_WIRE_3);
b2v_inst1:
ftctrl
PORTMAP(CLKK=>CLK,
CNT_EN=>SYNTHESIZED_WIRE_1,
RST_CNT=>SYNTHESIZED_WIRE_0,
Load=>SYNTHESIZED_WIRE_2);
b2v_inst2:
reg32b
PORTMAP(LK=>SYNTHESIZED_WIRE_2,
DIN=>SYNTHESIZED_WIRE_3,
DOUT=>DOUT);
ENDbdf_type;
RTL文件:
图98位十六进制频率计RTL文件
仿真结果:
图108位十六进制频率计仿真结果
第八章作业
8—5.在不改变原代码功能的条件下用两种方法改写例8-2,使其输出的控制信号(ALE、START、OE、LOCK)没有毛刺。
方法1:
将输出信号锁存后输出;方法2:
使用状态码直接输出型状态机,并比较这三种状态机的特点。
方法一:
将输出信号锁存后输出
VHDL文件:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYADCINTIS
PORT(D:
INSTD_LOGIC_VECTOR(7DOWNTO0);--来自0809转换好的8位数据
CLK:
INSTD_LOGIC;--状态机工作时钟
EOC:
INSTD_LOGIC;--转换状态指示,低电平表示正在转换
ALE:
OUTSTD_LOGIC;--8个模拟信号通道地址锁存信号
START:
OUTSTD_LOGIC;--转换开始信号
OE:
OUTSTD_LOGIC;--数据输出三态控制信号
ADDA:
OUTSTD_LOGIC;--信号通道最低位控制信号
LOCK0:
OUTSTD_LOGIC;--观察数据锁存时钟
Q:
OUTSTD_LOGIC_VECTOR(7DOWNTO0));--8位数据输出
ENDADCINT;
ARCHITECTUREbehavOFADCINTIS
TYPEstatesIS(st0,st1,St2,st3,st4);--定义各状态子类型
SIGNALcurrent_state,next_state:
states:
=st0;
SIGNALREGL:
STD_LOGIC_VECTOR(7DOWNTO0);
SIGNALLOCK:
STD_LOGIC;--转换后数据输出锁存时钟信号
SIGNALALE0:
STD_LOGIC;--8个模拟信号通道地址锁存信号
SIGNALSTART0:
STD_LOGIC;--转换开始信号
SIGNALOE0:
STD_LOGIC;--数据输出三态控制信号
BEGIN
ADDA<='1';--当ADDA<='0',模拟信号进入通道IN0;当ADDA<='1',则进入通道INI
Q<=REGL;--LOCK0<=LOCK;
COM:
PROCESS(current_state,EOC,CLK)BEGIN--规定各状态转换方式
CASEcurrent_stateIS
WHENst0=>ALE0<='0';START0<='0';LOCK<='0';OE0<='0';
next_state<=st1;--0809初始化
WHENst1=>ALE0<='1';START0<='1';LOCK<='0';OE0<='0';
next_state<=st2;--启动采样
WHENst2=>ALE0<='0';START0<='0';LOCK<='0';OE0<='0';
IF(EOC='1')THENnext_state<=st3;--EOC=1表明转换结束
ELSEnext_state<=st2;ENDIF;--转换未结束,继续等待
WHENst3=>ALE0<='0';START0<='0';LOCK<='0';OE0<='1';
next_state<=st4;--开启OE,输出转换好的数据
WHENst4=>ALE0<='0';START0<='0';LOCK<='1';OE0<='1';next_state<=st0;
WHENOTHERS=>next_state<=st0;
ENDCASE;
IFCLK'EVENTANDCLK='1'THEN
ALE<=ALE0;START<=START0;LOCK0<=LOCK;OE<=OE0;--方法1:
信号锁存后输出
ENDIF;
ENDPROCESSCOM;
REG:
PROCESS(CLK)
BEGIN
IF(CLK'EVENTANDCLK='1')THENcurrent_state<=next_state;ENDIF;
ENDPROCESSREG;--由信号current_state将当前状态值带出此进程:
REG
LATCH1:
PROCESS(LOCK)--此进程中,在LOCK的上升沿,将转换好的数据锁入
BEGIN
IFLOCK='1'ANDLOCK'EVENTTHENREGL<=D;ENDIF;
ENDPROCESSLATCH1;
ENDbehav;
该程序的RTL文件:
图11方法一的RTL文件
仿真结果:
方法二:
使用状态码直接输出型状态机。
VHDL文件:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYAD0809IS
PORT(D:
INSTD_LOGIC_VECTOR(7DOWNTO0);
CLK,EOC:
INSTD_LOGIC;
ALE,START,OE,ADDA:
OUTSTD_LOGIC;
c_state:
OUTSTD_LOGIC_VECTOR(4DOWNTO0);
Q:
OUTSTD_LOGIC_VECTOR(7DOWNTO0));
ENDAD0809;
ARCHITECTUREbehavOFAD0809IS
SIGNALcurrent_state,next_state:
STD_LOGIC_VECTOR(4DOWNTO0);
CONSTANTst0:
STD_LOGIC_VECTOR(4DOWNTO0):
="00000";
CONSTANTst1:
STD_LOGIC_VECTOR(4DOWNTO0):
="11000";
CONSTANTst2:
STD_LOGIC_VECTOR(4DOWNTO0):
="00001";
CONSTANTst3:
STD_LOGIC_VECTOR(4DOWNTO0):
="00100";
CONSTANTst4:
STD_LOGIC_VECTOR(4DOWNTO0):
="00110";
SIGNALREGL:
STD_LOGIC_VECTOR(7DOWNTO0);
SIGNALLOCK:
STD_LOGIC;
BEGIN
ADDA<='1';Q<=REGL;START<=current_state(4);ALE<=current_state(3);
OE<=current_state
(2);LOCK<=current_state
(1);c_state<=current_state;
COM:
PROCESS(current_state,EOC)BEGIN--规定各状态转换方式
CASEcurrent_stateIS
WHENst0=>next_state<=st1;--0809初始化
WHENst1=>next_state<=st2;--启动采样
WHENst2=>IF(EOC='1')THENnext_state<=st3;--EOC=1表明转换结束
ELSEnext_state<=st2;--转换未结束,继续等待
ENDIF;
WHENst3=>next_state<=st4;--开启OE,输出转换好的数据
WHENst4=>next_state<=st0;
WHENOTHERS=>next_state<=st0;
ENDCASE;
ENDPROCESSCOM;
REG:
PROCESS(CLK)
BEGIN
IF(CLK'EVENTANDCLK='1')THENcurrent_state<=next_state;
ENDIF;
ENDPROCESSREG;--由信号current_state将当前状态值带出此进程:
REG
LATCH1:
PROCESS(LOCK)--此进程中,在LOCK的上升沿,将转换好的数据锁入
BEGIN
IFLOCK='1'ANDLOCK'EVENTTHENREGL<=D;
ENDIF;
ENDPROCESSLATCH1;
ENDbehav;
该程序的RTL文件:
图12方法二的RTL文件
仿真结果:
图13方法二对应的RTL文件
仿真结果:
图14方法二仿真结果
实验与设计
8—1.(4)将8位待测预置数作为外部输入信号,即可以随时改变序列检测器中的比较数据。
写出此程序的符号化单进程有限状态机。
程序设计如下:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYSCHK2IS
PORT(DIN,CLK,CLR:
INSTD_LOGIC;
SHR:
INSTD_LOGIC_VECTOR(7DOWNTO0);
AB:
OUTSTD_LOGIC_VECTOR(3DOWNTO0));
ENDENTITYSCHK2;
ARCHITECTUREbehavOFSCHK2IS
SIGNALQ:
INTEGERRANGE0TO8;
SIGNALD:
STD_LOGIC_VECTOR(7DOWNTO0);
BEGIN
D<=SHR;
PROCESS(CLK,CLR)
BEGIN
IFCLR='1'THENQ<=0;
ELSIFCLK'EVENTANDCLK='1'THEN
CASEQIS
WHEN0=>IFDIN=D(7)THENQ<=1;ELSEQ<=0;ENDIF;
WHEN1=>IFDIN=D(6)THENQ<=2;ELSEQ<=0;ENDIF;
WHEN2=>IFDIN=D(5)THENQ<=3;ELSEQ<=0;ENDIF;
WHEN3=>IFDIN=D(4)THENQ<=4;ELSEQ<=0;ENDIF;
WHEN4=>IFDIN=D(3)THENQ<=5;ELSEQ<=0;ENDIF;
WHEN5=>IFDIN=D
(2)THENQ<=6;ELSEQ<=0;ENDIF;
WHEN6=>IFDIN=D
(1)THENQ<=7;ELSEQ<=0;ENDIF;
WHEN7=>IFDIN=D(0)THENQ<=8;ELSEQ<=0;ENDIF;
WHENOTHERS=>Q<=0;
ENDCASE;
ENDIF;
ENDPROCESS;
PROCESS(Q)
BEGIN
IFQ=8THENAB<="1010";
ELSEAB<="1011";
ENDIF;
ENDPROCESS;
ENDARCHITECTUREbehav;
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