ADDA等一些芯片的verilog程序Word文档下载推荐.docx
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- 上传时间:2022-11-16
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ADDA等一些芯片的verilog程序Word文档下载推荐.docx
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input[7:
0]datain;
outputst;
outputale;
outputoe;
outputadclk;
output[7:
0]dataout;
regadclk;
reg[7:
regst;
regoe;
regale;
//frequencedividerforAD
parameterDiv_adclk=8'
d9;
//(9+1)*2=20adclk=2.5M
parameterDiv_clk_state=4'
d4;
//(4+1)*2=10clk_state=5M
reg[8:
0]div_cnt_ad;
//frequencedivcnt
reg[3:
0]div_cnt_state;
regclk_state;
always@(negedgeclkin)begin
if(div_cnt_ad!
=Div_adclk)
div_cnt_ad<
=div_cnt_ad+1'
b1;
elsebegin
=0;
adclk<
=~adclk;
end
if(div_cnt_state!
=Div_clk_state)
div_cnt_state<
=div_cnt_state+1'
clk_state<
=~clk_state;
end
end
/*ADconvert*/
0]state;
0]delay;
initialbegin
state<
=4'
d0;
always@(negedgeclk_state)begin
case(state)
4'
d0:
begin//clearall
st<
=1'
b0;
oe<
ale<
delay<
=8'
h00;
d1;
d1:
begin//alelatch
d2;
end
d2:
begin//strasing
d3;
d3:
begin//alefalling
d4:
begin//stfalling
d5;
d5:
begin//eocdelayafterst;
8clock+2us=26stata_clk
=delay+1'
if(delay==8'
d26)
d6;
else
d6:
begin//testeoc(convetefinished);
if(eoc)
d7;
else
d7:
begin//outenable
d8;
d8:
begin//takedata
dataout<
=datain;
d9:
begin//outunable;
return
default:
endcase
endmodule
clk=5MhzT=0.2us
thedistance=0.2*1000_000*data*340m/s
modulechao(clk,start,reset,trig,echo,data,success,time_out);
inputclk,start,reset,echo;
outputtrig,data,success,time_out;
regtrig,time_out,success;
reg[31:
0]data;
parameterPrepare=4'
parameterDelay_trig=4'
parameterEcho_raising=4'
parameterEcho_falling=4'
parameterTime_out=4'
parameterSuccess=4'
0]dely;
//60*0.2=12us
0]timer;
//iftimerisbiggerthan0x1e848(farthan4.0m),timeout
always@(negedgeclkornegedgereset)begin
if(!
reset)begin
=Prepare;
elsebegin
case(state)
Prepare:
begin
timer<
=32'
h0000_0000;
trig<
//success<
//time_out<
if(!
start)begin
//trigthedevice
dely<
b0000_0000;
state<
=Delay_trig;
end
elsebeginstate<
Delay_trig:
begin//delay12us
=dely+1'
if(dely!
d60)begin//60
elsebegin
//endoftrig
=Echo_raising;
end
Echo_raising:
begin//waitforechorassing
timer<
=timer+1'
if(echo)begintimer<
state<
=Echo_falling;
elsebeginstate<
/*if(timer>
d2250)begin//>
450us
end*/
Echo_falling:
begin//waitforechofallingortimeout
=timer+32'
if(timer>
d120000)begin//outof10m
state=Time_out;
if(!
echo)begin
data<
=timer;
=Success;
elsebegin
state<
end
Time_out:
time_out<
=~time_out;
Success:
success<
=~success;
begin
end//endofif
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