EDA电子设计自动化实验报告山东大学信息学院.docx
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EDA电子设计自动化实验报告山东大学信息学院.docx
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EDA电子设计自动化实验报告山东大学信息学院
实验任务:
四选一数据选择器设计
【连接电路图】:
【仿真波形】
【引脚配置】
实验任务:
四位比较器设计
【设计思路】
A、B是两个输入的二进制数,G代表大于(Greater)M代表等于(middle)L代表低于(low)
【实验代码】
libraryieee;
useieee.std_logic_1164.all;
entitycomp4is
port(A:
instd_logic_vector(3downto0);
B:
instd_logic_vector(3downto0);
G,L,M:
outstd_logic);
endcomp4;
architecturebehaveofcomp4is
begin
p1:
process(A,B)
begin
if(A>B)thenG<='1';M<='0';L<='0';
elsif(A
elseG<='0';M<='1';L<='0';
endif;
endprocessp1;
endbehave;
注:
建立的工程名必须与代码中主体名comp4一致,才能正常工作
【仿真波形】
【引脚配置】
实验任务:
四位加法器设计
【设计思路】
数a,b是两个四位二进制数,和放在sum里,溢出位是cout
【实验代码】
libraryieee;
useieee.std_logic_1164.all;
useIEEE.std_logic_unsigned.all;
entityaddis
port(a:
instd_logic_vector(3downto0);
b:
instd_logic_vector(3downto0)
cin:
instd_logic;
sum:
outstd_logic_vector(3downto0);
cout:
outstd_logic);
endadd;
architecturebehavofaddis
signalaa,bb,s:
std_logic_vector(4downto0);
begin
aa<='0'&a;
bb<='0'&b;
s<=aa+bb+cin;
sum<=s(3downto0);
cout<=s(4);
endbehav;
注:
建立的工程名必须与代码中主体名add一致,才能正常工作
作出仿真波形如下:
引脚配置如下:
实验任务:
七人表决器设计
【设计思路】
定义a是七位二进制数,表示七个人的表决结果,0是否定,1是肯定
如果有4个或以上的1,那么结果y就是1
遍历a的每一个数,每遇见一个1,i=i+1,当i≥4时,y=1
【实验代码】
libraryieee;
useieee.std_logic_1164.all;
entityvoteis
port(a:
instd_logic_vector(6downto0);
y:
outstd_logic);
endvote;
architecturebehavofvoteis
beginprocess(a)
variablei:
integer;
begini:
=0;
if(a(0)='1')theni:
=i+1;
endif;
if(a
(1)='1')theni:
=i+1;,
endif;
if(a
(2)='1')theni:
=i+1;
endif;
if(a(3)='1')theni:
=i+1;
endif;
if(a(4)='1')theni:
=i+1;
endif;
if(a(5)='1')theni:
=i+1;
endif;
if(a(6)='1')theni:
=i+1;
endif;
if(i>3)
theny<='1';
elsey<='0';
endif;
endprocess;
endbehav;
注:
建立的工程名必须与代码中主体名vote一致,才能正常工作
【仿真波形】
【引脚配置】
实验任务:
七段译码器(共阳极)
源代码如下:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entityqiduanyimais
port(
a:
instd_logic_vector(3downto0);
rst:
std_logic;
dataout:
outstd_logic_vector(6downto0));
endqiduanyima;
architectureoneofqiduanyimais
begin
process(a)
begin
caseais
when"0000"=>dataout<="1000000";
when"0001"=>dataout<="1111001";
when"0010"=>dataout<="0100100";
when"0011"=>dataout<="0110000";
when"0100"=>dataout<="0011001";
when"0101"=>dataout<="0010010";
when"0110"=>dataout<="0000010";
when"0111"=>dataout<="1111000";
when"1000"=>dataout<="0000000";
when"1001"=>dataout<="0010000";
whenothers=>dataout<="1111111";
endcase;
endprocess;
endone;
注:
建立的工程名必须与代码中主体名qiduanyima一致,才能正常工作
实验任务:
分频器设计
【实验代码】
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
Entitymy_clkis
port(in_clk:
instd_logic;
out_clk:
outstd_logic);
endmy_clk;
Architecturetoeofmy_clkis
Begin
counter:
process(in_clk)
Variablec1:
integer:
=0;
begin
if(in_clk'eventandin_clk='1'andc1<24999999)
thenc1:
=c1+1;
out_clk<='1';
elsif(in_clk'eventandin_clk='1'andc1<49999999)
thenc1:
=c1+1;
out_clk<='0';
elsif(in_clk'eventandin_clk='1'andc1=49999999)
thenc1:
=0;
out_clk<='1';
endif;
endprocesscounter;
endtoe;
注:
建立的工程名必须与代码中主体名my_clk一致,才能正常工作
【引脚配置】
实验任务:
十进制计数器设计
【源代码】
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityjishuqi10is
port(en:
instd_logic;
to0:
instd_logic;
clock:
instd_logic;
out10:
outstd_logic_vector(3downto0);
co:
outstd_logic);
end;
architectureoneofjishuqi10is
signalnum:
integerrange0to10;
begin
process(clock)
begin
ifen='1'then
ifclock'eventandclock='1'then
ifnum=9then
num<=0;
else
num<=num+1;
endif;
endif;
endif;
ifto0='0'then
num<=0;
endif;
ifnum=9then
co<='1';
else
co<='0';
endif;
casenumis
when1=>out10<="0001";
when2=>out10<="0010";
when3=>out10<="0011";
when4=>out10<="0100";
when5=>out10<="0101";
when6=>out10<="0110";
when7=>out10<="0111";
when8=>out10<="1000";
when9=>out10<="1001";
when0=>out10<="0000";
whenothers=>out10<="0000";
endcase;
endprocess;
end;
注:
建立的工程名必须与代码中主体名jishuqi10一致,才能正常工作
作出仿真波形如下:
保存并封装后,重新建立一个工程,把十进制译码器和七段译码管联合使用:
引脚配置如下:
实验任务:
百进制计数器设计
十进制封装后,保存并重新建立一个工程,连接成为100进制的计数器:
引脚配置如下:
实验任务:
巴克码发生器
源代码如下:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitybakemais
port(clk:
instd_logic;
bakema:
outstd_logic;
jp:
outstd_logic);
end;
architectureoneofbakemais
signalcount:
integerrange0to6;
begin
process(clk)
begin
jp<=clk;
ifclk'eventandclk='1'then
ifcount=6then
count<=0;
else
count<=count+1;
endif;
endif;
casecountis
when0=>bakema<='1';
when1=>bakema<='1';
when2=>bakema<='1';
when3=>bakema<='0';
when4=>bakema<='0';
when5=>bakema<='1';
when6=>bakema<='0';
whenothers=>bakema<='0';
endcase;
endprocess;
end;
注:
建立的工程名必须与代码中主体名bakema一致,才能正常工作
作出仿真波形如下:
引脚配置如下:
实验任务:
红绿灯设计
【设计思路】
东西方向和南北方向的代码大致相近
都是配置了50个状态(num)
红色(red)是状态26-50
绿色(gre)是状态6-25
黄色(yel)是状态1-5
当复位键按下(to0=1)时,南北方向会置状态50(红),东西置25(绿)
然后状态参数(num)每秒减一,不断循环
【实验代码】
南北方向芯片的代码:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitynanbeiis
port(en:
instd_logic;
to0:
instd_logic;
clock:
instd_logic;
out10:
outstd_logic_vector(3downto0);
out20:
outstd_logic_vector(3downto0);
red:
outstd_logic;
gre:
outstd_logic;
yel:
outstd_logic);
end;
architectureoneofnanbeiis
signalnum:
integerrange1to50;
begin
process(clock)
begin
ifen='1'then
ifclock'eventandclock='1'then
ifnum=1then
num<=50;
else
num<=num-1;
endif;
endif;
endif;
ifto0='0'then
num<=50;
endif;
ifnum>25then
red<='1';gre<='0';yel<='0';
elsifnum>5then
red<='0';gre<='1';yel<='0';
else
red<='0';gre<='0';yel<='1';
endif;
if44 out20<="0010"; elsif34 out20<="0001"; elsif25 out20<="0000"; elsif25=numthen out20<="0010"; elsif14 out20<="0001"; elsif5 out20<="0000"; elsif0 out20<="0000"; endif; casenumis when1=>out10<="0001"; when2=>out10<="0010"; when3=>out10<="0011"; when4=>out10<="0100"; when5=>out10<="0101"; when6=>out10<="0001"; when7=>out10<="0010"; when8=>out10<="0011"; when9=>out10<="0100"; when10=>out10<="0101"; when11=>out10<="0110"; when12=>out10<="0111"; when13=>out10<="1000"; when14=>out10<="1001"; when15=>out10<="0000"; when16=>out10<="0001"; when17=>out10<="0010"; when18=>out10<="0011"; when19=>out10<="0100"; when20=>out10<="0101"; when21=>out10<="0110"; when22=>out10<="0111"; when23=>out10<="1000"; when24=>out10<="1001"; when25=>out10<="0000"; when26=>out10<="0001"; when27=>out10<="0010"; when28=>out10<="0011"; when29=>out10<="0100"; when30=>out10<="0101"; when31=>out10<="0110"; when32=>out10<="0111"; when33=>out10<="1000"; when34=>out10<="1001"; when35=>out10<="0000"; when36=>out10<="0001"; when37=>out10<="0010"; when38=>out10<="0011"; when39=>out10<="0100"; when40=>out10<="0101"; when41=>out10<="0110"; when42=>out10<="0111"; when43=>out10<="1000"; when44=>out10<="1001"; when45=>out10<="0000"; when46=>out10<="0001"; when47=>out10<="0010"; when48=>out10<="0011"; when49=>out10<="0100"; when50=>out10<="0101"; whenothers=>out10<="0000"; endcase; endprocess; end; end; 注: 建立的工程名必须与代码中主体名nanbei一致,才能正常工作 东西方向芯片的代码如下 libraryieee; useieee.std_logic_1164.all; useieee.std_logic_unsigned.all; entitydongxiis port(en: instd_logic; to0: instd_logic; clock: instd_logic; out10: outstd_logic_vector(3downto0); out20: outstd_logic_vector(3downto0); red: outstd_logic; gre: outstd_logic; yel: outstd_logic); architectureoneofdongxiis signalnum: integerrange1to50; begin process(clock) begin ifen='1'then ifclock'eventandclock='1'then ifnum=1then num<=50; else num<=num-1; endif; endif; endif; ifto0='0'then num<=25; endif; ifnum>25then red<='1';gre<='0';yel<='0'; elsifnum>5then red<='0';gre<='1';yel<='0'; else red<='0';gre<='0';yel<='1'; endif; if44 out20<="0010"; elsif34 out20<="0001"; elsif25 out20<="0000"; elsif25=numthen out20<="0010"; elsif14 out20<="0001"; elsif5 out20<="0000"; elsif0 out20<="0000"; endif; casenumis when1=>out10<="0001"; when2=>out10<="0010"; when3=>out10<="0011"; when4=>out10<="0100"; when5=>out10<="0101"; when6=>out10<="0001"; when7=>out10<="0010"; when8=>out10<="0011"; when9=>out10<="0100"; when10=>out10<="0101"; when11=>out10<="0110"; when12=>out10<="0111"; when13=>out10<="1000"; when14=>out10<="1001"; when15=>out10<="0000"; when16=>out10<="0001"; when17=>out10<="0010"; when18=>out10<="0011"; when19=>out10<="0100"; when20=>out10<="0101"; when21=>out10<="0110"; when22=>out10<="0111"; when23=>out10<="1000"; when24=>out10<="1001"; when25=>out10<="0000"; when26=>out10<="0001"; when27=>out10<="0010"; when28=>out10<="0011"; when29=>out10<="0100"; when30=>out10<="0101"; when31=>out10<="0110"; when32=>out10<="0111"; when33=>out10<="1000"; when34=>out10<="1001"; when35=>out10<="0000"; when36=>out10<="0001"; when
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- 关 键 词:
- EDA 电子设计 自动化 实验 报告 山东大学 信息 学院