数字钟电路原理图程序.docx
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数字钟电路原理图程序.docx
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数字钟电路原理图程序
数字钟电路原理图程序清单
********顶层程序描述***********
程序:
TIMER_SET.VHD
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entitytimer_setis
port(cp:
instd_logic;--CLOCK
segout:
outstd_logic_vector(7downto0);--SEG7DISPLAYO/P
selout:
outstd_logic_vector(5downto0);--SELECTSEG7O/P
numout:
outstd_logic_vector(3downto0);
--NUMBERDISPLAYSIGNAL
key:
instd_logic_vector(2downto0));--TIMER&ADJUST&CLR
endtimer_set;
architecturebehavioraloftimer_setis
componentcounter60
port(cp:
instd_logic;
bin:
outstd_logic_vector(5downto0);
s:
instd_logic;
clr:
instd_logic;
ec:
instd_logic;
cy60:
outstd_logic);
endcomponent;
componentcounter24
port(cp:
instd_logic;
bin:
outstd_logic_vector(5downto0);
s:
instd_logic;
clr:
instd_logic;
ec:
instd_logic;
cy24:
outstd_logic);
endcomponent;
componentfree_counter
port(cp:
instd_logic;
dbs:
instd_logic_vector(5downto0);
dbm:
instd_logic_vector(5downto0);
dbh:
instd_logic_vector(5downto0);
state:
instd_logic_vector(1downto0);
sec:
outstd_logic;
sample:
outstd_logic;
glitter:
outstd_logic;
bin:
outstd_logic_vector(5downto0);
enb:
outstd_logic_vector(2downto0);
sel:
outstd_logic_vector(5downto0);
match:
outstd_logic;
s:
outstd_logic_vector(2downto0));
endcomponent;
componentbinary_bcd
port(bin:
instd_logic_vector(5downto0);
bcd:
outstd_logic_vector(7downto0));
endcomponent;
componentseven_segment
port(num:
instd_logic_vector(3downto0);
seg:
outstd_logic_vector(6downto0));
endcomponent;
componentdebounce
port(cp:
instd_logic;
sample:
instd_logic;
key:
instd_logic_vector(2downto0);
dly_out:
outstd_logic);
endcomponent;
componentdifferential
port(cp:
instd_logic;
dly_out:
instd_logic;
diff:
outstd_logic);
endcomponent;
componenttimerset
port(cp:
instd_logic;
diff:
instd_logic;
key:
instd_logic_vector(2downto0);
state:
outstd_logic_vector(1downto0));
endcomponent;
signalbin:
std_logic_vector(5downto0);--BINARYO/P
signaldbs:
std_logic_vector(5downto0);--BINARYSECO/P
signaldbm:
std_logic_vector(5downto0);--BINARYMINO/P
signaldbh:
std_logic_vector(5downto0);--BINARYHRO/P
signalenb:
std_logic_vector(2downto0);
--ENABLEHR&MIN&SECO/P
signalsec:
std_logic;--1HZ脉冲波形
signalbcd:
std_logic_vector(7downto0);
signalclr:
std_logic;--清楚信号
signalcys,cym,cyh:
std_logic;--小时、小时、HR进位信号
signals:
std_logic_vector(2downto0);--选择SEGMENT7
signalnum:
std_logic_vector(3downto0);--NUMBERDISPLAYSIGNAL
signalseg:
std_logic_vector(6downto0);--SEG7DISPLAYSIGNAL
signalsel:
std_logic_vector(5downto0);--SELECTSEG7SIGNAL
signalsample,dly_out,diff:
std_logic;--BINARY
signalstate:
std_logic_vector(1downto0);--TIMER设定状态
--11计时
--10调秒
--01调分
--00调时
signalmatch:
std_logic;
signalglitter:
std_logic;--闪烁
begin
connection:
block
signaladj,ecs,ecm,ech,sc:
std_logic;
begin
u1:
counter60portmap(cp,dbs,enb(0),clr,ecs,cys);
u2:
counter60portmap(cp,dbm,enb
(1),clr,ecm,cym);
u3:
counter24portmap(cp,dbh,enb
(2),clr,ech,cyh);
u4:
free_counterport
map(cp,dbs,dbm,dbh,state,sec,sample,glitter,bin,enb,sel,match,s);
u5:
binary_bcdportmap(bin,bcd);
u6:
seven_segmentportmap(num,seg);
u7:
debounceportmap(cp,sample,key,dly_out);
u8:
differentialportmap(cp,dly_out,diff);
u9:
timersetportmap(cp,diff,key,state);
clr<=notkey(0);--复位计时
sc<=state
(1)andstate(0);--计时状态
adj<=secand(notsc)andkey
(1);--adjust
ecs<=(secandsc)or(adjandstate
(1)andnotstate(0));--计秒
ecm<=(cysandsc)or(adjandnotstate
(1)andstate(0));--计分
ech<=(cymandsc)or(adjandnotstate
(1)andnotstate(0));--计时
selout<=sel;
gen:
foriin0to6generate
segout(i)<=seg(i)and(scor(glitterornotmatch));
endgenerate;
segout(7)<='0';
numout<=num;
endblockconnection;
select_bcd:
block
begin
num<=bcd(3downto0)when(s=0ors=2ors=4)else
bcd(7downto0);
endblockselect_bcd;
endbehavioral;
********子模块描述********
COUNTER24.VHD--24进制计数器模块
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entitycounter24is
port(cp:
instd_logic;--时钟脉冲
bin:
outstd_logic_vector(5downto0);--二进制
s:
instd_logic;--输出激活信号
clr:
instd_logic;--清除信号
ec:
instd_logic;--使能计数信号
cy24:
outstd_logic);--计数24进位信号
endcounter24;
architecturebehavioralofcounter24is
signalq:
std_logic_vector(4downto0);
signalrst,dly:
std_logic;
begin--计数24
process(cp,rst)
begin
ifrst='1'then
q<="00000";--复位计数器
elsifcp'eventandcp='1'then
dly<=q(4);
ifec='1'then
q<=q+1;--计数值加1
endif;
endif;
endprocess;
cy24<=notq(4)anddly;--进位信号微分
rst<='1'whenq=24orclr='1'else'0';--复位信号设定
bin<=('0'&q)whens='1'else"000000";--计数输出
endbehavioral;
COUNTER60.VHD--60进制计数器模块
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entitycounter60is
port(cp:
instd_logic;--时钟脉冲
bin:
outstd_logic_vector(5downto0);--二进制
s:
instd_logic;--输出激活信号
clr:
instd_logic;--清除信号
ec:
instd_logic;--使能计数信号
cy60:
outstd_logic);--计数60进位信号
endcounter60;
architecturebehavioralofcounter60is
signalq:
std_logic_vector(5downto0);
signalrst,dly:
std_logic;
begin--计数60
process(cp,rst)
begin
ifrst='1'then
q<="000000";--复位计数器
elsifcp'eventandcp='1'then
dly<=q(5);
ifec='1'then
q<=q+1;--计数值加1
endif;
endif;
endprocess;
cy60<=notq(5)anddly;--进位信号微分
rst<='1'whenq=60orclr='1'else--复位信号设定
'0';
bin<=qwhens='1'else--计数输出
"000000";
endbehavioral;
FREE_COUNTER.VHD--自由计数器&产生扫描信号
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entityfree_counteris
port(cp:
instd_logic;
dbs:
instd_logic_vector(5downto0);
dbm:
instd_logic_vector(5downto0);
dbh:
instd_logic_vector(5downto0);
state:
instd_logic_vector(1downto0);
sec:
outstd_logic;
sample:
outstd_logic;
glitter:
outstd_logic;
bin:
outstd_logic_vector(5downto0);
enb:
outstd_logic_vector(2downto0);
sel:
outstd_logic_vector(5downto0);
match:
outstd_logic;
s:
outstd_logic_vector(2downto0));
endfree_counter;
architecturebehavioraloffree_counteris
signalq:
std_logic_vector(24downto0);
signaldly,sdly:
std_logic;
signalss:
std_logic_vector(2downto0);
signalen:
std_logic_vector(2downto0);
begin--计数器计数
process(cp)
begin
ifcp'eventandcp='1'then
dly<=q(21);
sdly<=q(14);
q<=q+1;--计数
endif;
endprocess;
glitter<=q(21);
sec<=q(21)andnotdly;--微分产生1HZ
ss<=q(15downto13);--about250HZ
sample<=q(14)andnotsdly;--取样信号
--扫描信号
sel<="111110"whenss=0else
"111101"whenss=1else
"111001"whenss=2else
"110111"whenss=3else
"101111"whenss=4else
"011111"whenss=5else
"111111";
en<="001"when(ss=0orss=1)else
"010"when(ss=2orss=3)else
"100"when(ss=4orss=5)else
"000";
bin<=dbswhenen="001"else--选择秒、分、时
dbmwhenen="010"else
dbhwhenen="100"else
"000000";
match<='1'when((ss=0orss=1)andstate="10")else
'1'when((ss=2orss=3)andstate="01")else
'1'when((ss=4orss=5)andstate="00")else
'0';
s<=ss;
enb<=en;
endbehavioral;
BINARY_BCD.VHD--二进制与BCD码转换模块
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entitybinary_bcdis
port(bin:
instd_logic_vector(5downto0);
bcd:
outstd_logic_vector(7downto0););
endbinary_bcd;
architecturebehavioralofbinary_bcdis
begin--二进制与BCD码的转换
bcd<="00000000"whenbin=0else
"00000001"whenbin=1else
"00000010"whenbin=2else
"00000011"whenbin=3else
"00000100"whenbin=4else
"00000101"whenbin=5else
"00000110"whenbin=6else
"00000111"whenbin=7else
"00001000"whenbin=8else
"00001001"whenbin=9else
"00010000"whenbin=10else
"00010001"whenbin=11else
"00010010"whenbin=12else
"00010011"whenbin=13else
"00010100"whenbin=14else
"00010101"whenbin=15else
"00010110"whenbin=16else
"00010111"whenbin=17else
"00011000"whenbin=18else
"00011001"whenbin=19else
"00100000"whenbin=20else
"00100001"whenbin=21else
"00100010"whenbin=22else
"00100011"whenbin=23else
"00100100"whenbin=24else
"00100101"whenbin=25else
"00100110"whenbin=26else
"00100111"whenbin=27else
"00101000"whenbin=28else
"00101001"whenbin=29else
"00110000"whenbin=30else
"00110001"whenbin=31else
"00110010"whenbin=32else
"00110011"whenbin=33else
"00110100"whenbin=34else
"00110101"whenbin=35else
"00110110"whenbin=36else
"00110111"whenbin=37else
"00111000"whenbin=38else
"00111001"whenbin=39else
"01000000"whenbin=40else
"01000001"whenbin=41else
"01000010"whenbin=42else
"01000011"whenbin=43else
"01000100"whenbin=44else
"01000101"whenbin=45else
"01000110"whenbin=46else
"01000111"whenbin=47else
"01001000"whenbin=48else
"01001001"whenbin=49else
"01010000"whenbin=50else
"01010001"whenbin=51else
"01010010"whenbin=52else
"01010011"whenbin=53else
"01010100"whenbin=54else
"01010101"whenbin=55else
"01010110"whenbin=56else
"01010111"whenbin=57else
"01011000"whenbin=58else
"01011001"whenbin=59else
"00000000";
endbehavioral;
SEVEN_SEGMENT.VHD--七段数码显示模块
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entityseven_segmentis
port(num:
instd_logic_vector(3downto0);
seg:
outstd_logic_vector(6downto0));
endseven_segment;
architecturebehavioralofseven_segmentis--BinaryCode->Segment7Code
begin
seg<="0111111"whennum=0else
"0000110"whennum=1else
"1011011"whennum=2else
"1001111"whennum=3else
"1100
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