Pentium 4M 奔腾处理器分页原理.docx
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Pentium 4M 奔腾处理器分页原理.docx
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Pentium4M奔腾处理器分页原理
Understanding4MPageSizeExtensions
onthePentiumProcessor
by
RobertR.Collins
It'sbeenmorethanthreeyearssinceIntelfirstpublishedthePentiumFamilyUser'sManual.TheManualomitteddiscussionofsomenew,advancedprogrammingfeatures.Inteloriginallyplannedtoreleasethisinformationinitsmanuals,butinstead,putthisinformationinadocumentcommonlyreferredtoas"AppendixH"(formallyknownastheSupplementtothePentiumProcessorUser'sManual)andrequiredrecipientstosigna15-yearnondisclosureagreement(NDA).ThisdecisionhasbeenthefocusofacontroversyconcerningIntel'srighttoprotectitsintellectualpropertyversustherightsofallprogrammerstohaveaccesstoinformationthatwillbenefittheirprograms.AnotherpointofcontentionistheNDAitself.Intelclaimsthatanybodyneedingthisinformationwillneverbedeniedit,aslongastheysigntheNDA.ButseveralstorieshavecirculatedregardingprogrammersbeingdeniedbecauseIntelclaimstheydon'tneedtheinformation.ThishasspawnedacommunityofprogrammersdedicatedtoreverseengineeringthesefeaturesandpublishingtheirfindingsonInternetnewsgroupsandtheWorldWideWeb.Butisallofthisnecessary?
Intelhaspromisedthatthenot-yet-releasedPentiumProProcessorFamilyDeveloper'sManualwillcontaininformationonmanyoftheseadvancedfeatures,perhapsevenadescriptionof4-MBpaging.
Four-MBpagingallowstheoperatingsystemtoaccessverylargedatastructureswithoutconstantlyreferencingtheTranslationLookasideBuffer(TLB),whichisusedbytheprocessortocachevirtual-to-physicaladdresstranslationsforthemostrecentlyusedpagesofmemory.Thisfeatureismostusefultooperating-systemdeveloperswhowantasinglepageofmemorydedicatedtotheOSkerneloralargedatastructure,suchasavideo-framebuffer.Informationabout4-MBpaginghasbeenpubliclydocumentedbyIntel-butyouneedtoknowwheretolooktofindit,InordertogetacompletedescriptionofPentium's4-MBpages,youneedtoreadboththePentiumFamilyUser'sManual,Volume3(P/N241430)andthei860TMXPMicroprocessorDataBook(P/N240874).
InthePentiummanuals,thereareatleastninereferencesto4-MBpages.Thisisagoodstarttoreverseengineering4-MBpages.Thesereferencesgiveyouthenecessarycluestowritesoftwarethatunlocksthesecretsofpage-sizeextensions(PSE).However,suchaneffortisunnecessary.TheInteli860XPprocessordocumentationclaimsthei860XPispage-levelcompatiblewiththeIntel386,Intel486,andPentiumprocessors.Thiscompatibilityisnoteworthybecausethei860XPalsosupports4-MBpages,anditsdocumentationprovidesacompletedescriptionofthe4-MBpagingmechanism(seei860TMXPMicroprocessorDataBook,section2.4).Allthat'sneededtoobtainanAppendixHdescriptionof4-MBpagesareafewreferencesfromthePentiummanualsandthedescriptionof4-MBpagesfromthei860XPmanual.
A4-KBPageBackgrounder
Whenpagingisenabled,linearaddressesprogram-visibleaddresses)aremappedtohysicaladdresses(busaddresses).Pagingmakesitpossibletoexecuteprogramsmuchlargerthanthecomputer'savailableamountofmemory.Whenthemicroprocessorneedsmorememory,itgeneratesapagefaulttodemandthataportionofmemorybemappedbetweentheharddiskandmainmemory.Memoryispartitionedintocontiguousblocks,called"pageframes."Eachpageframeis4KB.ThePentiumpagingmechanismconsistsofthefollowing:
∙APageDirectoryBaseRegister(PDBR).
∙Apagedirectory.
∙Atleastonepagetable.
ThePDBRisCR3,andpointstothebaseofthepagedirectory.Eachpage-directoryentry(PDE)pointstothepagetablesfor4MBofmemory.ThePDEcontainscontrolinformationandthepointerstothepagetables.LikethePDE,eachpage-tableentry(PTE)containscontrolinformation,butpointstoa4-KBpageframe.Linearaddressesareconvertedtophysicaladdressesbyusinga20-bitpointerinapagetableandcombiningitwiththelow-order12bitsofthelinearaddresstoforma32-bitphysicaladdress.Forpurposesofconversion,thelinearaddressisbrokenintothreeparts:
∙Thehigh-order10bitsformanindexintothepagedirectory.
∙Thenext10bitsformanindexintothepagetable.
∙Theremaining12bitsareanindexintoapageframe.
Theupper20bitsofthePTEarethencombinedwiththelow-order12bitsofthelinearaddresstoformthephysicaladdress.Thereisadirectrelationshipbetweenthesizesofthesethreefieldsandthepagesize.Thelower12bitscanaddress212,or4KBofmemory.Hence,eachPTEcontrols4KBofmemory.TheamountofmemorycontrolledbyeachPDEisdeterminedbythenumberofaddressbitsusedasanindexintothepagetable,plusthenumberofbitsusedasthepage-frameindex.ThePTEindexis10bits,andthepage-frameindexis12bits,making222,or4MBofmemorycontrolledbyeachPDE.Thisassociationwillbeimportantinunderstandingthe4-MBpagingmechanism.Figure1showshowlinearaddressesaretranslatedtophysicaladdressesfor4-KBpages.
Figure1--PageTranslationfor4KBPageSizes
Makingthejumpto4MBpages
Withanunderstandingofthe4-KBpagingmechanism,it'snotdifficulttodeducethe4-MBpagingmechanism.Recallthateachpage-directoryentrycontrols4MBofmemory.NowimaginehowFigure1wouldlookifthepage-tablelookupwereeliminated.Thepage-frameindexwouldincreasefrom12bitsto22bits,thusallowingdirectcontrolofa4-MBpagesize.The20-bitpointerinthepagedirectorywouldbereducedtoa10-bitpointer,pointingdirectlytothe4-MBpageframeofmemory.Withthepage-tablelookupeliminated,thepagedirectorypointsdirectlytoa4-MBpageframe.Thisdescribeshow4-MBpagesareimplementedinthei860XP(i860?
XPMicroprocessorDataBook,section2.4).Butthequestionremains:
Are4-MBi860XPpagescompatiblewith4-MBPentiumpages?
Toanswerthatquestion,weneedtocomparethei860andPentiummanuals.
Thei860manualclaimsthatthei8604-KBpagingmechanismiscompatiblewiththex86implementation.Acomparisonofpage-directoryformatandpage-tableformatsubstantiatesthisclaim.Thepage-size(PS)bitofthei860pagedirectorysharesthesamelocationasthePentium'sPSbit(seei860?
XPMicroprocessorDataBook,Figure2.13).Withthisinformation,youcanassumetheyarecompatible,andlookmorecloselyatthePentiummanualforthemechanicsofenablingandusing4-MBpages.
Volume3ofthePentiummanualdescribeshowCR4.PSEenablesPSE'sand4-MBpages,butrefersyoutoAppendixHformoreinformation.LaterinthePentiummanual,bit7ofthePDEisidentifiedasthePSbit.WithoutCR4.PSE=1,thePentiumwillalwaysuseIntel486-compatible(4-KB)paging,regardlessofthesettingofthePDE.PSbit.Similarly,whenCR4.PSE=1,andPDE.PS=0,PentiumstillusesIntel486-compatible4-KBpages.ButwhenCR4.PSE=1,andPDE.PS=1,Pentiumusesani860XP-compatible4-MBpagingtranslation.
Thelinearaddressfora4-MBpageisconvertedtoaphysicaladdressinmuchthesamemanneras4-KBpages.However,theaccesstothepagetableisomitted.Thehigh-order10bitsformanindexintothepagedirectory.Thepagedirectorynolongercontainsa20-bitpointertoapagetable,butinsteadcontainsa10-bitpointertothe4-MBpageframeofmemory.Thisconventionmandatesthatall4-MBpagesresideon4-MBboundaries.The10-bitpointerinthepagedirectorytheniscombinedwiththelow-order22bitsofthelinearaddresstoformthe32-bitphysicaladdress.
Figure2describesthe4-MBand4-KBpagingtranslationmechanism.Ironically,Figure11-16inPentiumProcessorFamilyDeveloper'sManual,Volume3,1993edition,containedavirtuallyidenticalpicture.Intelobviouslyrecognizedthesignificanceofthispictorialrepresentationof4-MBpages.SubsequenteditionsofthePentiummanualweresubstantiallymodifiedtoremovethevisualrepresentationofthe4-MBpagingmechanism.
Figure2--PageTranslationfor4MBand4KBPageSizes
Side-effectsandCaveatsof4-MBPages
Thereareside-effectsandcaveatstoenabling4-MBpages.ConsiderthefollowingexcerptfromthePentiumProcessorFamilyDeveloper'sManual,Volume3,section23.2.14.1,whichdiscussescompatibilitywithpreviousIntelprocessors:
APageFaultexceptionoccurswhena1isdetectedinanyofthereservedbitpositionsofapagetableentry,pagedirectoryentry,orpagedirectorypointer*duringaddresstranslationbythePentiumprocessor.
Inotherwords,ifanyreservedbitinthePDEorPTEis1,apagefaultwilloccur.ThisdoesnotoccurwhenCR4.PSE=0,butdoeswhenPSE'sareenabled(CR4.PSE=1).[1]EverybitinCR4enablesabehavioralextensiontotheIntel486processor.Inessence,CR4bitsenable/disableincompatibilitieswiththeIntel486.Therefore,itisanaturalextensionofenabling4-MBpagestoenablemorerigoroustypecheckingofthePDEandPTE.Unfortunately,eventhen,theaforementionedreferenceisn'tcompletelyaccurate.Settingsomereservedbitsdoesgenerateanexception,whilesettingothersdoesnot.ThisbehaviorcontradictstheInteldocumentation.IfthePentiumwasoriginallyintendedtobehaveasdocumented,thenthedocumentationdidn'tgetmodifiedtoaccuratelyreflectthecorrectbehaviorwhenrelaxedtypecheckingforreservedbitswasimplemented.Table1showsallofthePentiumpagingstructures.AllpositionsinthePDEandPTEmarkedasreservedwillgenerateapage-faultexceptionwhenCR4.PSE=1.AllpositionsinCR3,thePDE,andPTEmarkedas"0"arereserved,butdon'tgenerateapagefaultwhenCR4.PSE=1.Table2describesthemeaningofallofthefieldslistedinTable1.
[*]Itmi
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