FPGA实现双向IO口与时钟芯片的例子Word格式文档下载.docx
- 文档编号:21736364
- 上传时间:2023-02-01
- 格式:DOCX
- 页数:16
- 大小:29.31KB
FPGA实现双向IO口与时钟芯片的例子Word格式文档下载.docx
《FPGA实现双向IO口与时钟芯片的例子Word格式文档下载.docx》由会员分享,可在线阅读,更多相关《FPGA实现双向IO口与时钟芯片的例子Word格式文档下载.docx(16页珍藏版)》请在冰豆网上搜索。
0]i;
reg[7:
0]isStart;
0]rData;
0]rLED;
always@(posedgeCLKornegedgeRSTn)
if(!
RSTn)
begin
i<
=4'
d0;
isStart<
=8'
rData<
rLED<
end
else
case(i)
0:
if(Done_Sig)beginisStart<
=i+1'
b1;
elsebeginisStart<
b1000_0000;
h00;
1:
b0100_0000;
={4'
d1,4'
d2};
2:
b0010_0000;
d2,4'
3:
b0001_0000;
4:
if(Done_Sig)beginrLED<
=Time_Read_Data[3:
0];
d4;
b0000_0010;
endcase
wireDone_Sig;
wire[7:
0]Time_Read_Data;
ds1302_moduleU1
(
.CLK(CLK),
.RSTn(RSTn),
.Start_Sig(isStart),
.Done_Sig(Done_Sig),
.Time_Write_Data(rData),
.Time_Read_Data(Time_Read_Data),
.RST(RST),
.SCLK(SCLK),
.SIO(SIO)
);
assignLED=rLED;
Endmodule
moduleds1302_module
Start_Sig,
Done_Sig,
Time_Write_Data,
Time_Read_Data,
SIO
input[7:
0]Start_Sig;
outputDone_Sig;
0]Time_Write_Data;
output[7:
0]Words_Addr;
0]Write_Data;
wire[1:
0]Access_Start_Sig;
cmd_control_moduleU1
.Start_Sig(Start_Sig),//input-fromtop
.Done_Sig(Done_Sig),//output-totop
.Time_Write_Data(Time_Write_Data),//input-fromtop
.Time_Read_Data(Time_Read_Data),//output-totop
.Access_Done_Sig(Access_Done_Sig),//input-fromU2
.Access_Start_Sig(Access_Start_Sig),//output-toU2
.Read_Data(Read_Data),//input-fromU2
.Words_Addr(Words_Addr),//output-toU2
.Write_Data(Write_Data)//output-toU2
0]Read_Data;
wireAccess_Done_Sig;
function_moduleU2
.Start_Sig(Access_Start_Sig),//input-fromU1
.Words_Addr(Words_Addr),//input-fromU1
.Write_Data(Write_Data),//input-fromU1
.Read_Data(Read_Data),//output-toU1
.Done_Sig(Access_Done_Sig),//output-toU1
.RST(RST),//output-totop
.SCLK(SCLK),//output-totop
.SIO(SIO)//output-totop
modulecmd_control_module
Access_Done_Sig,
Access_Start_Sig,
Read_Data,
Words_Addr,
Write_Data
inputAccess_Done_Sig;
output[1:
0]rAddr;
rAddr<
case(Start_Sig[7:
0])
8'
b1000_0000:
//Writeunprotect
beginrAddr<
={2'
b10,5'
d7,1'
b0};
b0100_0000:
//Writehour
d2,1'
=Time_Write_Data;
b0010_0000:
//Writeminit
d1,1'
b0001_0000:
//Writesecond
d0,1'
b0000_1000:
//Writeprotect
b0000_0100:
//Readhour
b1};
b0000_0010:
//Readminit
b0000_0001:
//Readsecond
reg[1:
0]rRead;
regisDone;
=2'
rRead<
b00;
isDone<
=1'
b0;
elseif(Start_Sig[7:
3])//Writeaction
0:
if(Access_Done_Sig)beginisStart<
b10;
1:
beginisDone<
2:
elseif(Start_Sig[2:
0])//Readaction
if(Access_Done_Sig)beginrRead<
=Read_Data;
b01;
assignDone_Sig=isDone;
assignTime_Read_Data=rRead;
assignAccess_Start_Sig=isStart;
assignWords_Addr=rAddr;
assignWrite_Data=rData;
modulefunction_module
Write_Data,
input[1:
parameterT0P5US=5'
d24;
//50M*(0.5e-6)-1=24
reg[4:
0]Count1;
Count1<
=5'
elseif(Count1==T0P5US)
elseif(Start_Sig[0]==1'
b1||Start_Sig[1]==1'
b1)
=Count1+1'
reg[5:
regrSCLK;
regrRST;
regrSIO;
regisOut;
always@(posedgeCLKornegedgeRSTn)
=6'
rSCLK<
rRST<
rSIO<
isOut<
elseif(Start_Sig[1])
beginrSCLK<
=Words_Addr;
1,3,5,7,9,11,13,15:
if(Count1==T0P5US)i<
elsebeginrSIO<
=rData[(i>
>
1)];
2,4,6,8,10,12,14,16:
elsebeginrSCLK<
17:
beginrData<
=Write_Data;
18,20,22,24,26,28,30,32:
1)-9];
19,21,23,25,27,29,31,33:
34:
beginrRST<
35:
36:
elseif(Start_Sig[0])
beginisOut<
if(Count1==T0P5US)begini<
rData[(i>
1)-9]<
=SIO;
assignRead_Data=rData;
assignRST=rRST;
assignSCLK=rSCLK;
assignSIO=isOut?
rSIO:
1'
bz;
endmodule
- 配套讲稿:
如PPT文件的首页显示word图标,表示该PPT已包含配套word讲稿。双击word图标可打开word文档。
- 特殊限制:
部分文档作品中含有的国旗、国徽等图片,仅作为作品整体效果示例展示,禁止商用。设计者仅对作品中独创性部分享有著作权。
- 关 键 词:
- FPGA 实现 双向 IO 时钟 芯片 例子