毕业设计论文单片机英文中文翻译论文Word格式文档下载.docx
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毕业设计论文单片机英文中文翻译论文Word格式文档下载.docx
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CompatiblewithMCS-51Products
8KBytesofIn-SystemProgrammableISPFlashMemory–Endurance10000WriteEraseCycles
40Vto55VOperatingRange
FullyStaticOperation0Hzto33MHz
Three-levelProgramMemoryLock
256x8-bitInternalRAM
32ProgrammableIOLines
Three16-bitTimerCounters
EightInterruptSources
FullDuplexUARTSerialChannel
Low-powerIdleandPower-downModes
InterruptRecoveryfromPower-downMode
WatchdogTimerDualDataPointer
Power-offFlagFastProgrammingTime
FlexibleISPProgrammingByteandPageMode
GreenPbHalide-freePackagingOption
Description
TheAT89S52isalow-powerhigh-performanceCMOS8-bitmicrocontrollerwith8Kbytesofin-systemprogrammableFlashmemoryThedeviceismanufacturedusingAtmelshigh-densitynonvolatilememorytechnologyandiscompatiblewiththeindus-try-standard80C51instructionsetandpinoutTheon-chipFlashallowstheprogrammemorytobereprogrammedin-systemorbyaconventionalnonvolatilememorypro-grammerBycombiningaversatile8-bitCPUwithin-systemprogrammableFlashonamonolithicchiptheAtmelAT89S52isapowerfulmicrocontrollerwhichprovidesahighly-flexibleandcost-effectivesolutiontomanyembeddedcontrolapplications
TheAT89S52providesthefollowingstandardfeatures8KbytesofFlash256bytesofRAM32IOlinesWatchdogtimertwodatapointersthree16-bittimercountersasix-vectortwo-levelinterruptarchitectureafullduplexserialporton-chiposcillatorandclockcircuitryInadditiontheAT89S52isdesignedwithstaticlogicforoperationdowntozerofrequencyandsupportstwosoftwareselectablepowersavingmodesTheIdleModestopstheCPUwhileallowingtheRAMtimercountersserialportandinterruptsystemtocontinuefunctioningThePower-downmodesavestheRAMcon-tentsbutfreezestheoscillatordisablingallotherchipfunctionsuntilthenextinterruptorhardwarereset
PinDescription
21VCCSupplyvoltage
22GNDGround
23Port0Port0isan8-bitopendrainbidirectionalIOportAsanoutputporteachpincansinkeightTTLinputsWhen1sarewrittentoport0pinsthepinscanbeusedashigh-impedanceinputsPort0canalsobeconfiguredtobethemultiplexedlow-orderaddressdatabusduringaccessestoexternalprogramanddatamemoryInthismodeP0hasinternalpull-upsPort0alsoreceivesthecodebytesduringFlashprogrammingandoutputsthecodebytesdur-ingprogramverificationExternalpull-upsarerequiredduringprogramverification
24Port1Port1isan8-bitbidirectionalIOportwithinternalpull-upsThePort1outputbufferscansinksourcefourTTLinputsWhen1sarewrittentoPort1pinstheyarepulledhighbytheinter-nalpull-upsandcanbeusedasinputsAsinputsPort1pinsthatareexternallybeingpulledlowwillsourcecurrentIILbecauseoftheinternalpull-upsInadditionP10andP11canbeconfiguredtobethetimercounter2externalcountinputP10T2andthetimercounter2triggerinputP11T2EXrespectivelyasshowninthefollow-ingtable
Port1alsoreceivesthelow-orderaddressbytesduringFlashprogrammingandverification
PortPinAlternateFunctionsP10T2externalcountinputtoTimerCounter2clock-outP11T2EXTimerCounter2capturereloadtriggeranddirectioncontrolP15MOSIusedforIn-SystemProgrammingP16MISOusedforIn-SystemProgrammingP17SCKusedforIn-SystemProgramming25Port2Port2isan8-bitbidirectionalIOportwithinternalpull-upsThePort2outputbufferscansinksourcefourTTLinputsWhen1sarewrittentoPort2pinstheyarepulledhighbytheinter-nalpull-upsandcanbeusedasinputsAsinputsPort2pinsthatareexternallybeingpulledlowwillsourcecurrentIILbecauseoftheinternalpull-upsPort2emitsthehigh-orderaddressbyteduringfetchesfromexternalprogrammemoryanddur-ingaccessestoexternaldatamemorythatuse16-bitaddressesMOVXDPTRInthisapplicationPort2usesstronginternalpull-upswhenemitting1sDuringaccessestoexternaldatamemorythatuse8-bitaddressesMOVXRIPort2emitsthecontentsoftheP2SpecialFunctionRegisterPort2alsoreceivesthehigh-orderaddressbitsandsomecontrolsignalsduringFlashprogram-mingandverification
26Port3Port3isan8-bitbidirectionalIOportwithinternalpull-upsThePort3outputbufferscansinksourcefourTTLinputsWhen1sarewrittentoPort3pinstheyarepulledhighbytheinter-nalpull-upsandcanbeusedasinputsAsinputsPort3pinsthatareexternallybeingpulledlowwillsourcecurrentIILbecauseofthepull-upsPort3receivessomecontrolsignalsforFlashprogrammingandverificationPort3alsoservesthefunctionsofvariousspecialfeaturesoftheAT89S52asshowninthefol-lowingtable
PortPinAlternateFunctionsP30RXDserialinputportP31TXDserialoutputportP32externalinterrupt0P33externalinterrupt1P34T0timer0externalinputP35T1timer1externalinputP36externaldatamemorywritestrobeP37externaldatamemoryreadstrobe27RSTResetinputAhighonthispinfortwomachinecycleswhiletheoscillatorisrunningresetsthedeviceThispindriveshighfor98oscillatorperiodsaftertheWatchdogtimesoutTheDISRTObitinSFRAUXRaddress8EHcanbeusedtodisablethisfeatureInthedefaultstateofbitDISRTOtheRESETHIGHoutfeatureisenabled
28ALEAddressLatchEnableALEisanoutputpulseforlatchingthelowbyteoftheaddressduringaccessestoexternalmemoryThispinisalsotheprogrampulseinputduringFlashprogrammingInnormaloperationALEisemittedataconstantrateof16theoscillatorfrequencyandmaybeusedforexternaltimingorclockingpurposesNotehoweverthatoneALEpulseisskippeddur-ingeachaccesstoexternaldatamemoryIfdesiredALEoperationcanbedisabledbysettingbit0ofSFRlocation8EHWiththebitsetALEisactiveonlyduringaMOVXorMOVCinstructionOtherwisethepinisweaklypulledhighSettingtheALE-disablebithasnoeffectifthemicrocontrollerisinexternalexecutionmode
29ProgramStoreEnableisthereadstrobetoexternalprogrammemoryWhentheAT89S52isexecutingcodefromexternalprogrammemoryisactivatedtwiceeachmachinecycleexceptthattwoactivationsareskippedduringeachaccesstoexter-naldatamemory
210VPPExternalAccessEnablemustbestrappedtoGNDinordertoenablethedevicetofetchcodefromexternalprogrammemorylocationsstartingat0000HuptoFFFFHNotehoweverthatiflockbit1isprogrammedwillbeinternallylatchedonresetshouldbestrappedtoVCCforinternalprogramexecutionsThispinalsoreceivesthe12-voltprogrammingenablevoltageVPPduringFlashprogramming
211XTAL1Inputtotheinvertingoscillatoramplifierandinputtotheinternalclockoperatingcircuit
212XTAL2Outputfromtheinvertingoscillatoramplifier
MemoryOrganization
MCS-51deviceshaveaseparateaddressspaceforProgramandDataMemoryUpto64KbyteseachofexternalProgramandDataMemorycanbeaddressed
31ProgramMemory
IfthepinisconnectedtoGNDallprogramfetchesaredirectedtoexternalmemoryOntheAT89S52ifisconnectedtoVCCprogramfetchestoaddresses0000Hthrough1FFFHaredirectedtointernalmemoryandfetchestoaddresses2000HthroughFFFFHaretoexternalmemory
32DataMemory
TheAT89S52implements256bytesofon-chipRAMTheupper128bytesoccupyaparalleladdressspacetotheSpecialFunctionRegistersThismeansthattheupper128byteshavethesameaddressesastheSFRspacebutarephysicallyseparatefromSFRspaceWhenaninstructionaccessesaninternallocationaboveaddress7FHtheaddressmodeusedintheinstructionspecifieswhethertheCPUaccessestheupper128bytesofRAMortheSFRspaceInstructionswhichusedirectaddressingaccesstheSFRspaceForexamplethefollowingdirectaddressinginstructionaccessestheSFRatlocation0A0HwhichisP2
MOV0A0Hdata
Instructionsthatuseindirectaddressingaccesstheupper128bytesofRAMForexamplethefollowingindirectaddressinginstructionwhereR0contains0A0Haccessesthedatabyteataddress0A0HratherthanP2whoseaddressis0A0H
MOVR0data
Notethatstackoperationsareexamplesofindirectaddressingsotheupper128bytesofdataRAMareavailableasstackspace
WatchdogTimerOne-timeEnabledwithReset-out
TheWDTisintendedasarecoverymethodinsituationswheretheCPUmaybesubjectedtosoftwareupsetsTheWDTconsistsofa14-bitcounterandtheWatchdogTimerResetWDTRSTSFRTheWDTisdefaultedtodisablefromexitingresetToenabletheWDTausermustwrite01EHand0E1HinsequencetotheWDTRSTregisterSFRlocation0A6HWhentheWDTisenableditwillincrementeverymachinecyclewhiletheoscillatorisrunningTheWDTtimeoutperiodisdependentontheexternalclockfrequencyThereisnowaytodisabletheWDTexceptthroughreseteitherhardwareresetorWDToverflowresetWhenWDTover-flowsitwilldriveanoutputRESETHIGHpulseattheRSTpin
41UsingtheWDT
ToenabletheWDTausermustwrite01EHand0E1HinsequencetotheWDTRSTregisterSFRlocation0A6HWhentheWDTisenabledtheuserneedstoserviceitbywriting01EHand0E1HtoWDTRSTtoavoidaWDToverflowThe14-bitcounteroverflowswhenitreaches163833FFFHandthiswillresetthedeviceWhentheWDTisenableditwillincrementeverymachinecyclewhiletheoscillatorisrunningThismeanstheusermustresettheWDTatleastevery16383machinecyclesToresettheWDTtheusermustwrite01EHand0E1HtoWDTRSTWDTRSTisawrite-onlyregisterTheWDTcountercannotbereadorwrittenWhenWDToverflowsitwillgenerateanoutputRESETpulseattheRSTpinTheRESETpulsedura-tionis98xTOSCwher
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