eda作业.docx
- 文档编号:8193278
- 上传时间:2023-01-29
- 格式:DOCX
- 页数:18
- 大小:313.67KB
eda作业.docx
《eda作业.docx》由会员分享,可在线阅读,更多相关《eda作业.docx(18页珍藏版)》请在冰豆网上搜索。
eda作业
3,4
(2)四选一选择器
1、程序
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYMUX41AIS
PORT(D3,D2,D1,D0,EN:
INSTD_LOGIC;
A:
INSTD_LOGIC_VECTOR(1DOWNTO0);
Y:
OUTSTD_LOGIC);
ENDENTITYMUX41A;
ARCHITECTUREONEOFMUX41AIS
BEGIN
Y<=D0WHENA="00"ANDEN='0'ELSE
D1WHENA="01"ANDEN='0'ELSE
D2WHENA="10"ANDEN='0'ELSE
D3WHENA="11"ANDEN='0'ELSE
'Z';
ENDARCHITECTUREONE;
2、仿真波形
(3)八选一选择器
1程序
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYMUX81AIS
PORT(D7,D6,D5,D4,D3,D2,D1,D0,EN:
INSTD_LOGIC;
A:
INSTD_LOGIC_VECTOR(2DOWNTO0);
Y:
OUTSTD_LOGIC);
ENDENTITYMUX81A;
ARCHITECTUREONEOFMUX81AIS
BEGIN
Y<=D0WHENA="000"ANDEN='1'ELSE
D1WHENA="001"ANDEN='1'ELSE
D2WHENA="010"ANDEN='1'ELSE
D3WHENA="011"ANDEN='1'ELSE
D4WHENA="100"ANDEN='1'ELSE
D5WHENA="101"ANDEN='1'ELSE
D6WHENA="110"ANDEN='1'ELSE
D7WHENA="111"ANDEN='1'ELSE
'Z';
ENDARCHITECTUREONE;
2.仿真波形
(2)3/8译码器
1、程序
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYDECODER38AIS
PORT(A2,A1,A0,S3,S2,S1:
INSTD_LOGIC;
Y:
OUTSTD_LOGIC_VECTOR(7DOWNTO0));
ENDENTITYDECODER38A;
ARCHITECTUREONEOFDECODER38AIS
SIGNALP:
STD_LOGIC_VECTOR(5DOWNTO0);
BEGIN
P<=A2&A1&A0&S1&S2&S3;
WITHPSELECT
Y<="11111110"WHEN"000100",
"11111101"WHEN"001100",
"11111011"WHEN"010100",
"11110111"WHEN"011100",
"11101111"WHEN"100100",
"11011111"WHEN"101100",
"10111111"WHEN"110100",
"01111111"WHEN"111100",
"11111111"WHENOTHERS;
ENDONE;
2.仿真波形图
(3)七段显示译码器
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYDISPLY_DECODERIS
PORT(A:
INSTD_LOGIC_VECTOR(3DOWNTO0);
DOUT:
OUTSTD_LOGIC_VECTOR(6DOWNTO0));
ENDENTITYDISPLY_DECODER;
ARCHITECTUREONEOFDISPLY_DECODERIS
BEGIN
WITHASELECT
DOUT<="1000000"WHEN"0000",
"1111001"WHEN"0001",
"0100100"WHEN"0010",
"0110000"WHEN"0011",
"0011001"WHEN"0100",
"0010110"WHEN"0101",
"0000110"WHEN"0110",
"1111000"WHEN"0111",
"0000000"WHEN"1000",
"0010000"WHEN"1001",
"1111111"WHENOTHERS;
ENDONE;
G
F
E
D
C
B
A
g
f
e
d
c
b
a
0
1
0
0
0
0
0
0
1
1
1
1
1
0
0
1
2
0
1
0
0
1
0
0
3
0
1
1
0
0
0
0
4
0
0
1
1
0
0
1
5
0
0
1
0
1
1
0
6
0
0
0
0
1
1
0
7
1
1
1
1
0
0
0
8
0
0
0
0
0
0
0
9
0
0
1
0
0
0
0
5
(1)D触发器
程序:
libraryieee;
useieee.std_logic_1164.all;
entitydff1is
port(clk:
instd_logic;
d:
instd_logic;
clr:
instd_logic;
set:
instd_logic;
q:
outstd_logic);
enddff1;
architecturebhvofdff1is
begin
process(clk,clr,set)
begin
ifclr='1'thenq<='0';
elsifclk'eventandclk='1'
then
ifset='0'thenq<='1';
elseq<=d;
endif;
endif;
endprocess;
endbhv;
仿真波形
(2)同步清零异步置数的D触发器
libraryieee;
useieee.std_logic_1164.all;
entitydff2is
port(clk:
instd_logic;
d:
instd_logic;
clr:
instd_logic;
set:
instd_logic;
q:
outstd_logic);
enddff2;
architecturebhvofdff2is
begin
process(clk,clr,set)
begin
ifset='1'thenq<='1';
elsifclk'eventandclk='1'
then
ifclr='0'thenq<='0';
elseq<=d;
endif;
endif;
endprocess;
endbhv;
(3)JK触发器
Entitydff3is
Port(r,s,clk,J,K:
inbit;
Q:
outbit);
Enddff3;
Architecturethreeofdff3is
signalp:
bit;
Begin
process(r,s,clk,J,K)
Begin
if(r='1')thenp<='0';
elsif(clk'eventandclk='1')then
if(s='0')thenp<='1';
else
case(J&K)is
when"00"=>p<=p;
when"01"=>p<='0';
when"10"=>p<='1';
when"11"=>p<=notp;
Endcase;
Endif;
Endif;
Endprocess;
Q<=p;
Endthree;
思考题:
RS触发器
libraryieee;
useieee.std_logic_1164.all;
entityrsffis
port(r,s:
instd_logic;
q,qb:
outstd_logic);
endrsff;
architecturertlofrsffis
signalq_temp,qb_temp:
std_logic;
begin
process(r,s)
begin
if(s='1'andr='0')then
q_temp<='0';
qb_temp<='1';
elsif(s='0'andr='1')then
q_temp<='1';
qb_temp<='0';
elsif(s='1'andr='1')then
q_temp<=q_temp;
qb_temp<=qb_temp;
else
q_temp<='Z';
qb_temp<='Z';
endif;
endprocess;
q<=q_temp;
qb<=qb_temp;
endrtl;
6
(1)10进制计数器
(2)74160计数器
(3)24进制计数器
(4)75进制计数器
(5)156进制计数器
思考题
256分频
部分放大图形
全局图形
SimulationpaperofEDAExamination
(1)
NOTE:
Allthedesignmustbecompletedoncomputerinanhour,whencompleted,pleaseinformtheteacherforinspection.
Examinationsites:
EDALaboratory
Question1:
Youmaydesigna3to8decoder(nameddecoder38a,shownasFig.1)withVHDL,whichhas3decodinginputports(A2,A1,A0),8outputports(Y7,Y6Y5,Y4,Y3,Y2Y1,Y0).AndyoumayusetheQUARTUSII6.0softwaretocompletethecompilationandthesimulationofyourdesign.(50points)
Fig.13to8decoder
Question2:
Youmaydesigna#68BCDcounter(namedCDU_68,shownasFig.2)withVHDL,whichhasarising-edgeclockinputport(CLK),ahigh-levelcarryingoutport(COUT)andtwoBCDcodeoutputports(Q2[3..0],Q1[3..0]).AndyoumayusetheQUARTUSII6.0softwaretocompletethecompilationandthesimulationofyourdesign.(50points)
Fig.2#68counter
SimulationpaperofEDAExamination
(2)
NOTE:
Allthedesignmustbecompletedoncomputerinanhour,whencompleted,pleaseinformtheteacherforinspection.
Examinationsites:
EDALaboratory
Question1:
Youmaydesignabinarydisplaydecoder(nameddisplay4_7,shownasFig.1)withVHDL,whichhas4-bitbinary(0000~1111)inputports(A[3..0]),7segmenttypecodeoutputports(a,b,c,d,e,f,g).AndyoumayusetheQUARTUSII6.0softwaretocompletethecompilationandthesimulationofyourdesign.(50points)
Fig.1binarydisplaydecoder
Question2:
Youmaydesigna#35binarycounter(namedCOUNT_35,shownasFig.2)withVHDL,whichhasarising-edgeclockinputport(CLK),ahigh-levelcarrying-outport(COUT)anda6-bitoutputports(Q[5..0]).AndyoumayusetheQUARTUSII6.0softwaretocompletethecompilationandthesimulationofyourdesign.(50points)
Fig.2#35binarycounter
SimulationpaperofEDAExamination(3)
NOTE:
Allthedesignmustbecompletedoncomputerinanhour,whencompleted,pleaseinformtheteacherforinspection.
Examinationsites:
EDALaboratory
Question1:
Youmaydesigna6to1multiplexer(namedMUX61B,shownasFig.1)withVHDL,whichhas3controlinputports(A2,A1,A0),6datainputports(D5,D4,D3,D2,D1,D0),andadataoutputport(Q).AndyoumayusetheQUARTUSII6.0softwaretocompletethecompilationandthesimulationofyourdesign.(50points)
Fig.16to1multiplexer
Question2:
YoumaydesignaDflip-flop(namedDFF_A,shownasFig.2)withVHDL,whichhasaDinputport,anasynchronoushigh-levelresetinputport(RST),afalling-edgeclockinputport(CLK),and2outputports(Q,NQ).AndyoumayusetheQUARTUSII6.0softwaretocompletethecompilationandthesimulationofyourdesign.(50points)
- 配套讲稿:
如PPT文件的首页显示word图标,表示该PPT已包含配套word讲稿。双击word图标可打开word文档。
- 特殊限制:
部分文档作品中含有的国旗、国徽等图片,仅作为作品整体效果示例展示,禁止商用。设计者仅对作品中独创性部分享有著作权。
- 关 键 词:
- eda 作业