FPGASVM程序.docx
- 文档编号:5151654
- 上传时间:2022-12-13
- 格式:DOCX
- 页数:40
- 大小:21.62KB
FPGASVM程序.docx
《FPGASVM程序.docx》由会员分享,可在线阅读,更多相关《FPGASVM程序.docx(40页珍藏版)》请在冰豆网上搜索。
FPGASVM程序
//支持向量机顶层模块
moduleSVM_Little(clk,rst,Rd,Wr,Clkin,DATA);
inputclk;
inputrst;
inputRd;
inputWr;
inputClkin;
inout[9:
0]DATA;
wire[9:
0]Data_out;
wire[9:
0]Data_in;
assignDATA=Rd?
Data_out:
10'hzz;
assignData_in=Wr?
DATA:
10'hzz;
wirein1,in2,in3,in4,in5;
wirestart;
wire[16:
0]y;
wireenable_o;
//与单片机通信,并实现串转并。
MPU_commpu_comunication(.clk(clk),
.rst(rst),
.Rd(Rd),
.Wr(Wr),
.Clkin(Clkin),
.DATA(Data_in),
.x1(in1),
.x2(in2),
.x3(in3),
.x4(in4),
.x5(in5),
.start(start));
//生成支持向量查表地址
wire[7:
0]addr1,addr2;
wireLU_EN;
Addr_LUP_SVsAddr_Gen(.clk(clk),
.rst(clk),
.start(start),
.addr1(addr1),
.addr2(addr2),
.enable(LU_EN));
//查到2路支持向量,每组支持向量5个元素
wire[16:
0]x11,x21,x31,x41,x51;
wire[16:
0]x12,x22,x32,x42,x52;
wireMUL_EN;
LUP_SVshehe(.clk(clk),.rst(rst),.addr1(addr1),.addr2(addr2),.enable(LU_EN),
.x11(x11),.x21(x21),.x31(x31),.x41(x41),.x51(x51),
.x12(x12),.x22(x21),.x32(x31),.x42(x42),.x52(x51),
.Enable_o(MUL_EN));
//当前值与支持向量做减法
wire[16:
0]r11,r21,r31,r41,r51;
wire[16:
0]r12,r22,r32,r42,r52;
SUB_X_SVsub1(.in1(in1),.in2(in2),.in3(in3),.in4(in4),.in5(in5),
.x11(x11),.x21(x21),.x31(x31),.x41(x41),.x51(x51),
.x12(x12),.x22(x22),.x32(x32),.x42(x42),.x52(x52),
.r11(r11),.r21(r21),.r31(r31),.r41(r41),.r51(r51),
.r12(r12),.r22(r22),.r32(r32),.r42(r42),.r52(r52)
);
//求矩阵模2路
wire[19:
0]sum1,sum2;
wireMUL_G_EN1;
wireMUL_G_EN2;
MUL_ADD_5MUL_1(.clki(clk),.rst(rst),.enable(MUL_EN),
.a1(r11),.a2(r21),.a3(r31),.a4(r41),.a5(r51),
.sum(sum1),.enable_o(MUL_G_EN1));
MUL_ADD_5MUL_2(.clki(clk),.rst(rst),.enable(MUL_EN),
.a1(r12),.a2(r22),.a3(r32),.a4(r42),.a5(r52),
.sum(sum2),.enable_o(MUL_G_EN2));
//矩阵模乘伽玛值得到查exp表输入//两路
wireTA_E_EN1,TA_E_EN2;
wire[16:
0]data1,data2;
Mul_gammaM_A1(.clk(clk),
.rst(rst),
.enable(MUL_G_EN1),
.sum(sum1),
.data(data1),
.enable_o(TA_E_EN1));
Mul_gammaM_A2(.clk(clk),
.rst(rst),
.enable(MUL_G_EN2),
.sum(sum2),
.data(data2),
.enable_o(TA_E_EN2));
wire[16:
0]Exp_a,Exp_b;
wireADD_EN1,ADD_EN2;
wireSTA_A1,STA_A2;
Taylor_ET_E1(.clki(clk),
.rst(rst),
.enable(TA_E_EN1),
.x(data1),
.y(Exp_a),
.enable_o(ADD_EN1),
.start_o(STA_A1));
Taylor_ET_E2(.clki(clk),
.rst(rst),
.enable(TA_E_EN2),
.x(data2),
.y(Exp_b),
.enable_o(ADD_EN2),
.start_o(STA_A2));
SVs_MUL_AADD_end(.clk(clk),
.rst(rst),
.start(STA_A1),
.x1(Exp_a),
.x2(Exp_b),
.y(y));
assignenable_o=ADD_EN1;
assignData_out=y[16:
7];
endmodule
//与单片机通信接口模块
moduleMPU_com(clk,rst,Rd,Wr,Clkin,DATA,x1,x2,x3,x4,x5,start);
inputclk;
inputrst;
inputRd;
inputWr;
inputClkin;
input[9:
0]DATA;
output[15:
0]x1,x2,x3,x4,x5;
outputstart;
wire[9:
0]Data_in;
wire[15:
0]x1,x2,x3,x4,x5;
//assignDATA=Rd?
Data_out:
10'hzz;
assignData_in=Wr?
DATA:
10'hzz;
wirerdreq;
wire[9:
0]qout;
wire[2:
0]Wrused;
wirewrclk;
FIFO1buffer(
.data(Data_in),
.rdclk(clk),
.rdreq(rdreq),
.wrclk(wrclk),
.wrreq(Wr),
.q(qout),
.wrusedw(Wrused));
assignwrclk=Clkin|(rdreq?
clk:
1'b0);
Serial2ParellS2P(.clk(clk),.rst(rst),.Rd(rdreq),.Datain(qout),.Wrused(Wrused),.x1(x1),.x2(x2),.x3(x3),.x4(x4),.x5(x5),.start(start));
Endmodule
//读FIFO串专并模块
moduleSerial2Parell(clk,rst,Rd,Datain,Wrused,x1,x2,x3,x4,x5,start);
inputclk;
inputrst;
input[9:
0]Datain;
input[2:
0]Wrused;
outputRd;
output[15:
0]x1,x2,x3,x4,x5;
outputstart;
reg[15:
0]x1_r,x2_r,x3_r,x4_r,x5_r;
parameterIDLE=2'b0;
parameterRDST=2'd1;
parameterCCLT=2'd2;
parameterSTOP=2'd3;
reg[7:
0]PaData[4:
0];
reg[1:
0]state;
regRd_r;
reg[3:
0]i;
always@(posedgeclkornegedgerst)
if(!
rst)
begin
Rd_r<=1'b0;
i<=4'd0;
state<=IDLE;
x1_r<=15'b0;
x2_r<=15'b0;
x3_r<=15'b0;
x4_r<=15'b0;
x5_r<=15'b0;
end
else
case(state)
IDLE:
begin
if(Wrused==5)
begin
Rd_r<=1'b1;
state<=RDST;
end
else
state<=state;
end
RDST:
begin
if(i==4'd6)
begin
i=4'd0;
state<=CCLT;
Rd_r<=1'b0;
end
else
begin
x1_r<=Datain;
x2_r<=x1_r;
x3_r<=x2_r;
x4_r<=x3_r;
x5_r<=x4_r;
i<=i+1'b1;
end
end
CCLT:
begin
state<=STOP;
end
STOP:
begin
state<=IDLE;
end
default:
state<=IDLE;
endcase
assignRd=Rd_r;
assignx1=(state==CCLT)?
x1_r:
x1;
assignx2=(state==CCLT)?
x2_r:
x2;
assignx3=(state==CCLT)?
x3_r:
x3;
assignx4=(state==CCLT)?
x4_r:
x4;
assignx5=(state==CCLT)?
x5_r:
x5;
assignstart=(state==STOP)?
1'b1:
1'b0;
endmodule
//通信FIFO模块
`timescale1ps/1ps
//synopsystranslate_on
moduleFIFO1(
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
wrusedw);
input[9:
0]data;
inputrdclk;
inputrdreq;
inputwrclk;
inputwrreq;
output[9:
0]q;
output[2:
0]wrusedw;
wire[9:
0]sub_wire0;
wire[2:
0]sub_wire1;
wire[9:
0]q=sub_wire0[9:
0];
wire[2:
0]wrusedw=sub_wire1[2:
0];
dcfifodcfifo_component(
.data(data),
.rdclk(rdclk),
.rdreq(rdreq),
.wrclk(wrclk),
.wrreq(wrreq),
.q(sub_wire0),
.wrusedw(sub_wire1),
.aclr(),
.rdempty(),
.rdfull(),
.rdusedw(),
.wrempty(),
.wrfull());
defparam
dcfifo_component.intended_device_family="CycloneIVE",
dcfifo_component.lpm_numwords=8,
dcfifo_component.lpm_showahead="OFF",
dcfifo_component.lpm_type="dcfifo",
dcfifo_component.lpm_width=10,
dcfifo_component.lpm_widthu=3,
dcfifo_component.overflow_checking="ON",
dcfifo_component.rdsync_delaypipe=4,
dcfifo_component.underflow_checking="ON",
dcfifo_component.use_eab="ON",
dcfifo_component.wrsync_delaypipe=4;
endmodule
//支持向量机查找表地址生成模块
moduleAddr_LUP_SVs(clk,rst,start,addr1,addr2,enable);
inputclk;
inputrst;
inputstart;
output[7:
0]addr1;
output[7:
0]addr2;
outputenable;
reg[7:
0]cnt1,cnt2;
always@(posedgeclkornegedgerst)
if(!
rst)
begin
cnt1<=8'b0;
cnt2<=8'b0;
end
elseif(start)
begin
cnt1<=8'b0;
cnt2<=8'd128;
end
elseif(cnt1==8'd94)
begin
cnt1<=8'b0;
cnt2<=8'd128;
end
else
begin
cnt1<=cnt1+8'b1;
cnt2<=cnt2+8'b1;
end
regenable_r,enable_r_r;
always@(posedgeclkornegedgerst)
if(!
rst)
begin
enable_r<=1'b0;
enable_r_r<=1'b0;
end
elseif(start)
enable_r<=1'b1;
elseif(cnt1==8'd94)
enable_r<=1'b0;
else
begin
enable_r<=enable;
enable_r_r<=enable_r;
end
assignenable=enable_r;
assignaddr1=cnt1;
assignaddr2=cnt2;
endmodule
//支持向量表1存放模块X11_rom.v
//synopsystranslate_off
`timescale1ps/1ps
//synopsystranslate_on
moduleX11_rom(
address_a,
address_b,
clock,
enable,
q_a,
q_b);
input[7:
0]address_a;
input[7:
0]address_b;
inputclock;
inputenable;
output[15:
0]q_a;
output[15:
0]q_b;
`ifndefALTERA_RESERVED_QIS
//synopsystranslate_off
`endif
tri1clock;
tri1enable;
`ifndefALTERA_RESERVED_QIS
//synopsystranslate_on
`endif
wire[15:
0]sub_wire0;
wire[15:
0]sub_wire1;
wiresub_wire2=1'h0;
wire[15:
0]sub_wire3=16'h0;
wire[15:
0]q_b=sub_wire0[15:
0];
wire[15:
0]q_a=sub_wire1[15:
0];
altsyncramaltsyncram_component(
.clock0(clock),
.wren_a(sub_wire2),
.address_b(address_b),
.clocken0(enable),
.data_b(sub_wire3),
.wren_b(sub_wire2),
.address_a(address_a),
.data_a(sub_wire3),
.q_b(sub_wire0),
.q_a(sub_wire1)
//synopsystranslate_off,
.aclr0(),
.aclr1(),
.addressstall_a(),
.addressstall_b(),
.byteena_a(),
.byteena_b(),
.clock1(),
.clocken1(),
.clocken2(),
.clocken3(),
.eccstatus(),
.rden_a(),
.rden_b()
//synopsystranslate_on
);
defparam
altsyncram_component.address_reg_b="CLOCK0",
altsyncram_component.clock_enable_input_a="NORMAL",
altsyncram_component.clock_enable_input_b="NORMAL",
altsyncram_component.clock_enable_output_a="NORMAL",
altsyncram_component.clock_enable_output_b="NORMAL",
altsyncram_component.indata_reg_b="CLOCK0",
`ifdefNO_PLI
altsyncram_component.init_file="X11.rif"
`else
altsyncram_component.init_file="X11.hex"
`endif,
altsyncram_component.intended_device_family="CycloneIVE",
altsyncram_component.lpm_type="altsyncram",
altsyncram_component.numwords_a=256,
altsyncram_component.numwords_b=256,
altsyncram_component.operation_mode="BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a="NONE",
altsyncram_component.outdata_aclr_b="NONE",
altsyncram_component.outdata_reg_a="CLOCK0",
altsyncram_component.outdata_reg_b="CLOCK0",
altsyncram_component.power_up_uninitialized="FALSE",
altsyncram_component.widthad_a=8,
altsyncram_component.widthad_b=8,
altsyncram_component.width_a=16,
altsyncram_component.width_b=16,
altsyncram_component.width_byteena_a=1,
altsyncram_component.width_byteena_b=1,
altsyncram_component.wrcontrol_wraddress_reg_b="CLOCK0";
endmodule
//支持向量表2存放模块X21_rom
//synopsystranslate_off
`timescale1ps/1ps
//synopsystranslate_on
moduleX21_rom(
address_a,
address_b,
clock,
enable,
q_a,
q_b);
input[7:
0]address_a;
input[7:
0]address_b;
inputclock;
inputenable;
output[15:
0]q_a;
output[15:
0]q_b;
`ifndefALTERA_RESERVED_QIS
//synopsystranslate_off
`endif
tri1clock;
tri1enable;
`ifndefALTERA_RESERVED_QIS
//synopsystranslate_on
`endif
wire[15:
0]sub_wire0;
wire[15:
0]sub_wire1;
wiresub_wire2=1'h0;
wire[15:
0]sub_wire3=16'h0;
wire[15:
0]q_b=sub_wire0[15:
0];
wire[15:
0]q_a=sub_wire1[15:
0];
altsyncramaltsyncram_component(
.clock0(clock),
.wren_a(sub_wire2),
.address_b(address_b),
.clocken0(enable),
.data_b(sub_wire3),
.wren_b(sub_wire2),
.address_a(address_a),
.data_a(sub_wire3),
.q_b(sub_wire0),
.q_a(sub_wire1)
- 配套讲稿:
如PPT文件的首页显示word图标,表示该PPT已包含配套word讲稿。双击word图标可打开word文档。
- 特殊限制:
部分文档作品中含有的国旗、国徽等图片,仅作为作品整体效果示例展示,禁止商用。设计者仅对作品中独创性部分享有著作权。
- 关 键 词:
- FPGASVM 程序