华北电力大学科技学院EDA试验代码.docx
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华北电力大学科技学院EDA试验代码.docx
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华北电力大学科技学院EDA试验代码
实验一
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYhalf_adderIS
PORT(a:
INSTD_LOGIC;
b:
INSTD_LOGIC;
s:
OUTSTD_LOGIC;
c:
OUTSTD_LOGIC);
ENDENTITYhalf_adder;
ARCHITECTURErtlOFhalf_adderIS
BEGIN
s<=aXORb;
c<=aANDb;
ENDARCHITECTURErtl;
实验二
1
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYd_ffIS
PORT(
d:
INSTD_LOGIC;
clk:
INSTD_LOGIC;
q:
OUTSTD_LOGIC);
ENDENTITYd_ff;
ARCHITECTURErt1OFd_ffIS
BEGIN
PROCESS(clk)IS
BEGIN
IFclk'EVENTANDclk='1'THEN
q<=d;
ENDIF;
ENDPROCESS;
ENDARCHITECTURErt1;
2
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYshift_reg8IS
GENERIC(N:
INTEGER:
=8);
PORT(a,clk:
INSTD_LOGIC;
b:
OUTSTD_LOGIC);
ENDENTITYshift_reg8;
ARCHITECTURErt1OFshift_reg8IS
COMPONENTd_ffIS
PORT(
d:
INSTD_LOGIC;
clk:
INSTD_LOGIC;
q:
OUTSTD_LOGIC);
ENDCOMPONENTd_ff;
SIGNALs:
STD_LOGIC_VECTOR(1to(N-1));
BEGIN
g1:
FORIin0TO(N-1)GENERATE
g2:
IFi=0GENERATE
dffx:
d_ffPORTMAP(a,clk,s(i+1));
ENDGENERATE;
g3:
IFi=(N-1)GENERATE
dffx:
d_ffPORTMAP(s(i),clk,b);
ENDGENERATE;
g4:
IF((i/=0)AND(i/=N-1))GENERATE
dffx:
d_ffPORTMAP(s(i),clk,s(i+1));
ENDGENERATE;
ENDGENERATE;
ENDARCHITECTURErt1;
实验三:
过程的输出参数做信号使用
1:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
PACKAGEmy_vhdl_pacIS
PROCEDUREmax(a,b:
INstd_logic_vector(7downto0);
signaly:
OUTstd_logic_vector(7downto0));
ENDPACKAGEmy_vhdl_pac;
PACKAGEBODYmy_pacIS
PROCEDUREmax(a,b:
INstd_logic_vector(7downto0);
signaly:
OUTstd_logic_vector(7downto0)IS
BEGIN
IF(a
y<=b;
ELSE
y<=a;
ENDIF;
ENDPROCEDUREmax;
ENDPACKAGEBODYmy_vhdl_pac;
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEWORKmy_vhdl_pac.ALL;
ENTITYcompIS
PORT(d1:
INSTD_LOGIC_VECTOR(7DWONTO0);
d2:
INSTD_LOGIC_VECTOR(7DWONTO0);
rt:
:
OUTSTD_LOGIC_VECTOR(7DWONTO0));
ENDENTITYcomp;
ARCHITECTURErtlOFcompIS
BEGIN
max(d1,d2,rt);
ENDARCHITECTURErtl;
过程做变量
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
PACKAGEmy_vhdl_pacIS
PROCEDUREmax(a,b:
INstd_logic_vector(7downto0);
signaly:
OUTstd_logic_vector(7downto0));
ENDPACKAGEmy_vhdl_pac;
PACKAGEBODYmy_pacIS
PROCEDUREmax(a,b:
INstd_logic_vector(7downto0);
signaly:
OUTstd_logic_vector(7downto0))IS
BEGIN
IF(a
y:
=b;
ELSE
y:
=a;
ENDIF;
ENDPROCEDUREmax;
ENDPACKAGEBODYmy_vhdl_pac;
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEWORKmy_vhdl_pac.ALL;
ENTITYcompIS
PORT(d1:
INSTD_LOGIC_VECTOR(7DWONTO0);
d2:
INSTD_LOGIC_VECTOR(7DWONTO0);
rt:
:
OUTSTD_LOGIC_VECTOR(7DWONTO0));
ENDENTITYcomp;
ARCHITECTURErtlOFcompIS
BEGIN
PROCESS(d1,d2)IS
VARIABLEtmp:
STD_LOGIC_VECTOR(7DWONTO0);
BEGIN
max(d1,d2,tmp);
rt<=tmp;
ENDPROCESS;
ENDARCHITECTURErtl;
2:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYtype_convIS
PORT(a:
ININTEGERRANGE0TO9;
b:
INSTD_LOGIC_VECTOR(3DOWNTO0);
c:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
d:
OUTINTEGERRANGE0TO9);
ENDENTITYtype_conv;
ARCHITECTURErtlOFtype_convIS
BEGIN
c<=CONV_STD_LOGIC_VECTOR(a,4);
d<=CONV_INTEGER(b);
ENDARCHITECTURErtl;
实验四(都是同步复位)
1信号做计数器
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYcnt6IS
PORT(clk:
INSTD_LOGIC;
dout:
OUTINTEGERRANGE0TO5);
ENDENTITYcnt6;
ARCHITECTURErtlOFcnt6IS
SIGNALtmp:
INTEGERRANGE0TO5:
=0;
BEGIN
PROCESS(clk)IS
BEGIN
IFclk'EVENTANDclk='1'THEN
IFtmp=5THEN
tmp<=0;
ELSE
tmp<=tmp+1;
ENDIF;
ENDIF;
dout<=tmp;
ENDPROCESS;
ENDARCHITECTURErtl;
2变量作计数器
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYcnt6IS
PORT(clk:
INSTD_LOGIC;
dout:
OUTINTEGERRANGE0TO5);
ENDENTITYcnt6;
ARCHITECTURErtlOFcnt6IS
BEGIN
PROCESS(clk)IS
VARIABLEtmp:
INTEGERRANGE0TO5:
=0;
BEGIN
IFclk'EVENTANDclk='1'THEN
IFtmp=5THEN
tmp:
=0;
ELSE
tmp:
=tmp+1;
ENDIF;
ENDIF;
dout<=tmp;
ENDPROCESS;
ENDARCHITECTURErtl;
实验五
1
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYfull_adderIS
PORT(a,b,c:
INSTD_LOGIC;
s,co:
OUTSTD_LOGIC);
ENDENTITYfull_adder;
ARCHITECTURErtlOFfull_adderIS
SIGNALa_n,b_n,c_n:
STD_LOGIC;
SIGNALm1,m2,m3,m4,m5,m6,m7:
STD_LOGIC;
BEGIN
a_n<=NOTa;
b_n<=NOTb;
c_n<=NOTc;
m1<=a_nANDb_nANDc;
m2<=a_nANDbANDc_n;
m3<=a_nANDbANDc;
m4<=aANDb_nANDc_n;
m5<=aANDb_nANDc;
m6<=aANDbANDc_n;
m7<=aANDbANDc;
s<=m1ORm2ORm4ORm7;
co<=m3ORm5ORm6ORm7;
ENDARCHITECTURErtl;
2
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
USEIEEE.STD_LOGIC_ARITH.ALL;
ENTITYaluIS
PORT(a,b:
INSTD_LOGIC_VECTOR(3DOWNTO0);
c,d:
OUTSTD_LOGIC_VECTOR(4DOWNTO0);
e:
OUTSTD_LOGIC_VECTOR(7DOWNTO0);
f:
OUTSTD_LOGIC_VECTOR(4DOWNTO0));
ENDENTITYalu;
ARCHITECTURErtlOFaluIS
SIGNALt1,t2,t3:
INTEGER;
BEGIN
t1<=CONV_INTEGER(a);
t2<=CONV_INTEGER(b);
c<='0'&a+b;
d<='0'&a-b;
e<=a*b;
t3<=t1/t2;
f<=CONV_STD_LOGIC_VECTOR(t3,5);
ENDARCHITECTURErtl;
实验六
1八选一数据选择器CASE
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYmun_8_1IS
PORT(e_n,d0,d1,d2,d3,d4,d5,d6,d7,s2,s1,s0:
INSTD_LOGIC;
y,y_n:
OUTSTD_LOGIC);
ENDENTITYmun_8_1;
ARCHITECTURErtlOFmun_8_1IS
SIGNALsel:
STD_LOGIC_VECTOR(2DOWNTO0);
SIGNALtmp:
STD_LOGIC;
BEGIN
sel<=s2&s1&s0;
PROCESS(d0,d1,d2,d3,d4,d5,d6,d7,sel)IS
BEGIN
CASE(sel)IS
WHEN"000"=>tmp<=d0;
WHEN"001"=>tmp<=d1;
WHEN"010"=>tmp<=d2;
WHEN"011"=>tmp<=d3;
WHEN"100"=>tmp<=d4;
WHEN"101"=>tmp<=d5;
WHEN"110"=>tmp<=d6;
WHEN"111"=>tmp<=d7;
WHENOTHERS=>tmp<='X';
ENDCASE;
ENDPROCESS;
PROCESS(tmp,e_n)IS
BEGIN
IFe_n='0'THEN
y<=tmp;
y_n<=NOTtmp;
ELSE
y<='0';
y<='1';
ENDIF;
ENDPROCESS;
ENDARCHITECTURErtl;
1:
八位八选一数据选择器CASE
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYmux_8_1IS
PORT(d0,d1,d2,d3,d4,d5,d6,d7:
INSTD_LOGIC_VECTOR(7DOWNTO0);
e_n,s2,s1,s0:
INSTD_LOGIC;
y,y_n:
OUTSTD_LOGIC_VECTOR(7DOWNTO0));
ENDENTITYmux_8_1;
ARCHITECTURErtlOFmux_8_1IS
SIGNALsel:
STD_LOGIC_VECTOR(2DOWNTO0);
SIGNALtmp:
STD_LOGIC_VECTOR(7DOWNTO0);
BEGIN
sel<=s2&s1&s0;
PROCESS(d0,d1,d2,d3,d4,d5,d6,d7,sel)IS
BEGIN
CASE(sel)IS
WHEN"000"=>tmp<=d0;
WHEN"001"=>tmp<=d1;
WHEN"010"=>tmp<=d2;
WHEN"011"=>tmp<=d3;
WHEN"100"=>tmp<=d4;
WHEN"101"=>tmp<=d5;
WHEN"110"=>tmp<=d6;
WHEN"111"=>tmp<=d7;
WHENOTHERS=>tmp<="XXXXXXXX";
ENDCASE;
ENDPROCESS;
PROCESS(tmp,e_n)IS
BEGIN
IFe_n='0'THEN
y<=tmp;
y_n<=NOTtmp;
ELSE
y<="00000000";
y<="11111111";
ENDIF;
ENDPROCESS;
ENDARCHITECTURErtl;
2八选一数据选择器IF
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYmux8IS
PORT(e_n,d0,d1,d2,d3,d4,d5,d6,d7,s2,s1,s0:
INSTD_LOGIC;
y,y_n:
OUTSTD_LOGIC);
ENDENTITYmux8;
ARCHITECTURErtlOFmux8IS
SIGNALsel:
STD_LOGIC_VECTOR(2DOWNTO0);
SIGNALtmp:
STD_LOGIC;
BEGIN
sel<=s2&s1&s0;
PROCESS(d0,d1,d2,d3,d4,d5,d6,d7,sel)IS
BEGIN
IF(sel="000")THEN
tmp<=d0;
ELSIF(sel="000")THEN
tmp<=d0;
ELSIF(sel="001")THEN
tmp<=d1;
ELSIF(sel="010")THEN
tmp<=d2;
ELSIF(sel="011")THEN
tmp<=d3;
ELSIF(sel="100")THEN
tmp<=d4;
ELSIF(sel="101")THEN
tmp<=d5;
ELSIF(sel="110")THEN
tmp<=d6;
ELSIF(sel="111")THEN
tmp<=d7;
ENDIF;
ENDPROCESS;
PROCESS(tmp,e_n)IS
BEGIN
IFe_n='0'THEN
y<=tmp;
y_n<=NOTtmp;
ELSE
y<='0';
y_n<='1';
ENDIF;
ENDPROCESS;
ENDARCHITECTURErtl;
八位八选一数据选择器IF
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYmux8IS
PORT(d0,d1,d2,d3,d4,d5,d6,d7:
INSTD_LOGIC_VECTOR(7DOWNTO0);
e_n,s2,s1,s0:
INSTD_LOGIC;
y,y_n:
OUTSTD_LOGIC_VECTOR(7DOWNTO0));
ENDENTITYmux8;
ARCHITECTURErtlOFmux8IS
SIGNALsel:
STD_LOGIC_VECTOR(2DOWNTO0);
SIGNALtmp:
STD_LOGIC_VECTOR(7DOWNTO0);
BEGIN
sel<=s2&s1&s0;
PROCESS(d0,d1,d2,d3,d4,d5,d6,d7,sel)IS
BEGIN
IF(sel="000")THEN
tmp<=d0;
ELSIF(sel="000")THEN
tmp<=d0;
ELSIF(sel="001")THEN
tmp<=d1;
ELSIF(sel="010")THEN
tmp<=d2;
ELSIF(sel="011")THEN
tmp<=d3;
ELSIF(sel="100")THEN
tmp<=d4;
ELSIF(sel="101")THEN
tmp<=d5;
ELSIF(sel="110")THEN
tmp<=d6;
ELSIF(sel="111")THEN
tmp<=d7;
ENDIF;
ENDPROCESS;
PROCESS(tmp,e_n)IS
BEGIN
IFe_n='0'THEN
y<=tmp;
y_n<=NOTtmp;
ELSE
y<=(others=>'0');
y_n<=(others=>'1');
ENDIF;
ENDPROCESS;
ENDARCHITECTURErtl;
实验七
1八选一数据选择器条件
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYmux_8_1IS
PORT(e_n,d0,d1,d2,d3,d4,d5,d6,d7,s2,s1,s0:
INSTD_LOGIC;
y,y_n:
OUTSTD_LOGIC);
ENDENTITYmux_8_1;
ARCHITECTURErtlOFmux_8_1IS
SIGNALsel:
STD_LOGIC_VECTOR(2DOWNTO0);
BEGIN
sel<=s2&s1&s0;
y<=d0WHENsel="000"ELSE
d1WHENsel="001"ELSE
d2WHENsel="010"ELSE
d3WHENsel="011"ELSE
d4WHENsel="100"ELSE
d5WHENsel="101"ELSE
d6WHENsel="110"ELSE
d7WHENsel="111"ELSE
'X';
ENDARCHITECTURErtl;
1.八位八选一数据选择器条件信号赋值
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYmux_8_1IS
PORT(d0,d1,d2,d3,d4,d5,d6,d7:
INSTD_LOGIC_VECTOR(7DOWNTO0);
s2,s1,s0:
INSTD_LOGIC;
y,y_n:
OUTSTD_LOGIC_VECTOR(7DOWNTO0));
ENDENTITYmux_8_1;
ARCHITECTURErtlOFmux_8_1IS
SIGNALsel:
STD_LOGIC_VECTOR(2DOWNTO0);
BEGIN
sel<=s2&s1&s0;
y<=d0WHENsel="000"ELSE
d1WHENsel="001"ELSE
d2WHENsel="010"ELSE
d3WHENsel="011"ELSE
d4WHENsel="100"ELSE
d5WHENsel="101"ELSE
d6WHENsel="110"ELSE
d7WHENsel="111"ELSE
"XXXXXXXX";
ENDARCHITECTURErtl;
2八选一数据选择器选择信号赋值
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYmux_8_1IS
PORT(e_n,d0,d1,d2,d3,d4,d5,d6,d7,s2,s1,s0:
INSTD_LOGIC;
y,y_n:
OUTSTD_LOGIC);
ENDENTITYmux_8_1;
ARCHITECTURErtlOFmux_8_1IS
SIGNALsel:
STD_LOGIC_VECTOR(2DOWNTO0);
BEGIN
sel<=s2&s1&s0;
WITHselSELECT
y<=d0WHEN"000",
d1WHEN"001",
d2WHEN"010",
d3WHEN"011",
d4WHEN"100",
d5WHEN"101",
d6WHEN"110",
d7WHEN"111",
'X'WHENOTHERS;
ENDARCHITECTURErtl;
2八位
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