数字逻辑课后第五章.docx
- 文档编号:9002057
- 上传时间:2023-02-02
- 格式:DOCX
- 页数:19
- 大小:107.62KB
数字逻辑课后第五章.docx
《数字逻辑课后第五章.docx》由会员分享,可在线阅读,更多相关《数字逻辑课后第五章.docx(19页珍藏版)》请在冰豆网上搜索。
数字逻辑课后第五章
第五章习题答案
1.画出与阵列编程点
解:
2.画出或阵列编程点
解:
3.与、或阵列均可编程,画出编程点解;
rr
A眞BBc丄
FiF2F3
4.4变量LUT编程
解:
A。
Ai
A2
A3
SOP输出
5.用VHDL写出4输入与门解:
源代码:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYand4IS
PORT(a,b,c,d:
INSTD_LOGIC;x:
OUTSTD_LOGIC);
ENDand4;
ARCHITECTUREand4_arcOFand4IS
BEGIN
xv=aANDbANDcANDd;
ENDand4_arq
6.用VHDL写出4输入或门
解:
源代码:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYor4IS
PORT(a,b,c,d:
INSTD_LOGIC;x:
OUTSTD_LOGIC);ENDor4;
ARCHITECTUREor4_arcOFor4IS
BEGIN
xv=aORbORcORd;
ENDor4_arc;
7.用VHDL写出SOP表达式
解:
源代码:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYsopIS
PORT(a,b,c,d,e,f:
INSTD_LOGIC;x:
OUTSTD_LOGIC);
ENDsop;
ARCHITECTUREsop_arcOFsopIS
BEGIN
xv=(aANDb)OR(cANDd)OR(eANDf);
ENDsop_arc;
8.用VHDL写出布尔表达式
解:
源代码:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYbooleanIS
PORT(a,b,c:
INSTD_LOGIC;f:
OUTSTD_LOGIC);
ENDboolean;
ARCHITECTUREboolean_arcOFbooleanIS
BEGIN
fv=(aOR(NOTb)ORc)AND(aORbOR(NOTc))AND
((NOTa)OR(NOTb)OR(NOTc));ENDboolean_arc;
9.用VHDL结构法写出SOP表达式
解:
源代码:
三输入与非门的逻辑描述
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYnand3IS
PORT(a,b,c:
INSTD_LOGIC;x:
OUTSTD_LOGIC);
ENDnand3;
ARCHITECTUREnand3_arcOFnand3IS
BEGIN
xv=NOT(aANDbANDc);
ENDnand3_arc;
――顶层结构描述文件
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYsopIS
PORT(in1,in2,in3,in4,in5,in6,in7,in8,in9:
INSTD_LOGIC;out4:
OUTSTD_LOGIC);
ENDsop;
ARCHITECTUREsop_arcOFsopIS
COMPONENTnand3
PORT(a,b,c:
INSTD_LOGIC;
x:
OUTSTD_LOGIC);
ENDCOMPONENT;
SIGNALout1,out2,out3:
STD_LOGIC;
BEGIN
u1:
nand3PORTMAP(in1,in2,in3,out1);
u2:
nand3PORTMAP(in4,in5,in6,out2);
u3:
nand3PORTMAP(in7,in8,in9,out3);
u4:
nand3PORTMAP(out1,out2,out3,out4);
ENDsop;
10.用VHDL数据流法写出SOP表达式
解:
源代码:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYsopIS
PORT(in1,in2,in3,in4,in5,in6,in7,in8,in9:
INSTD_LOGIC;out4:
OUTSTD_LOGIC);
ENDsop;
ARCHITECTUREsop_arcOFsopIS
BEGIN
out4v=(iniANDin2ANDin3)OR(in4ANDin5ANDin6)OR(in7ANDin8ANDin9);
ENDsop_arc;
13.用VHDL设计3-8译码器
解:
源代码:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYdecoder_3_to_8IS
PORT(a,b,c,g1,g2a,g2b:
INSTD_LOGIC;
y:
OUTSTD_LOGIC_VECTOR(7downto0));
ENDdecoder_3_to_8;
ARCHITECTURErt1OFdecoder_3_to_8IS
SIGNALindata:
STD_LOGIC_VECTOR(2downto0);
BEGIN
indatav=c&b&a;
PROCESS(indata,g1,g2a,g2b)
BEGIN
IF(g1=‘TANDg2a0'ANDg2bD'THEN
CASEindataIS
WHEN"000"=>yv="11111110";
WHEN"001"=>yv="11111101";
WHEN"010"=>yv="11111011";
WHEN"011"=>yv="11110111";
WHEN"100"=>yv="11101111";
WHEN"101"=>yv="11011111";
WHEN"110"=>yv="10111111";
WHENothers=>yv="01111111";
ENDCASE;
ELSE
yv="11111111;
ENDIF;
ENDPROCESS;
ENDrt1;
14.用VHDL设计七段显示译码器
解:
源代码:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYsegment7IS
PORT(xin:
INSTD_LOGIC_VECTOR(3downto0);lt,rbi:
INSTD_LOGIC;yout:
OUTSTD_LOGIC_VECTOR(6downto0);birbo:
INOUTSTD_LOGIC);
ENDsegment7;
ARCHITECTUREseg7448OFsegment7IS
SIGNALsig_xin:
STD_LOGIC_VECTOR(3downto0);BEGIN
sig_xinv=xin;
PROCESS(sig_xin,lt,rbi,birbo)
BEGIN
IF(birbo=')'THEN
youtv="0000000";
ELSIF(It='0'THEN
youtv="1111111";
birbov='T
ELSIF(rbi='A'NDsig_xin="0000")THEN
youtv="0000000";
birbov='0'
ELSIF(rbi='ANDsig_xin="0000")THEN
youtv="1111110";
birbo<='1'
ELSE
15.用VHDL设计8/3优先编码器解:
源代码:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYpriorityencoderIS
PORT(din:
INSTD_LOGIC_VECTOR(7downto0);ei:
INSTD_LOGIC;yout:
OUTSTD_LOGIC_VECTOR(2downto0);eo,gs:
OUTSTD_LOGIC);
ENDpriorityencoder;
ARCHITECTUREcod74148OFpriorityencoderISBEGIN
PROCESS(ei,din)
BEGIN
IF(ei='1'THEN
yout<="111";
eov=,1,
gs<='1'
ELSE
IF(din(7)='O'THEN
yout<="000";
eo<='1'
gs<='O'
ELSIF(din(6)='O'THEN
yout<="001";
eo<='1'
gs<='0'
ELSIF(din(5)='0'THEN
yout<="010";
eo<='1'
gs<='0'
ELSIF(din(4)='0'THEN
yout<="011";
eo<='1'
gs<='0'
ELSIF(din(3)='0'THEN
yout<="100";
eo<='1'
gs<='0'
ELSIF(din
(2)='0'THEN
yout<="101";
eo<='1'
gs<='0'
ELSIF(din
(1)='0'THEN
yout<="110";
eo<='1'
gsv=,;
ELSIF(din(0)—O'T)HENyoutv="111";
eov='1'gsv='O'
ELSIF(din="11111111")THENyoutv="111";
eov='O'gsv='1'
ENDIF
ENDIF
ENDPROCESS
ENDcod74148;
16.用VHDL设计BCD码至二进制码转换器
解:
源代码:
libraryieee;
useieee.std_logic_1164.all;
entitybcdtobiis
port(
bcdcode:
INSTD_LOGIC_VECTOR(7DOWNTOO);
start:
qbit:
instd_logic;
OUTSTD_LOGIC_VECTOR(3DOWNTOO)
end;
architecture
behavioralofbcdtobiis
begin
process(start)
begin
ifstart='0'then
casebcdcode(7downto0)is
when"00000000"=>qbit(3downto0)<="0000";when"00000001"=>qbit(3downto0)<="0001";when"00000010"=>qbit(3downto0)<="0010";when"00000011"=>qbit(3downto0)<="0011";when"00000100"=>qbit(3downto0)<="0100";when"00000101"=>qbit(3downto0)<="0101";when"00000110"=>qbit(3downto0)<="0110";when"00000111"=>qbit(3downto0)<="0111";when"00001000"=>qbit(3downto0)<="1000";
when"00001001"=>qbit(3downto0)<="1001";
when"00010000"=>qbit(3downto0)<="1010";
when"00010001"=>qbit(3downto0)<="1011";
when"00010010"=>qbit(3downto0)<="1100";
when"00010011"=>qbit(3downto0)<="1101";
when"00010100"=>qbit(3downto0)<="1110";
when"00010101"=>qbit(3downto0)<="1111";
whenothers=>qbit(3downto0)<="0000";endcase;
else
qbit(3downto0)<="0000";
endif;
endprocess;
endbehavioral;
17.用VHDL设计4位寄存器
解:
异步复位
源代码:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYregister_4IS
PORT(clk,r:
INSTD_LOGIC;
din:
INSTD_LOGIC_VECTOR(3downto0);qout:
OUTSTD_LOGIC_VECTOR(3downto0));ENDregister_4;
ARCHITECTURErge_arcOFregister_4IS
SIGNALq_temp:
STD_LOGIC_VECTOR(3downto0);BEGIN
PROCESS(clk,r)BEGIN
IF(r='1'THEN
q_tempv="0000";
ELSIF(elk'eventANDelk―1'T)HENq_tempv=din;
ENDIF;
qoutv=q_temp;
ENDPROCESS;
ENDrge_are;
18.用VHDL设计4位双向移位寄存器
解:
s1、s0控制工作方式,dsl为左移数据输入,dsr为右移数据输入。
源代码:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYshiftregIS
PORT(clk,r,dsr,dsl:
INSTD_LOGIC;s1,s0:
INSTD_LOGIC;--functionselectdin:
INSTD_LOGIC_VECTOR(3downto0);--datainqout:
OUTSTD_LOGIC_VECTOR(3downto0));--dataoutENDshiftreg;
ARCHITECTUREls74194OFshiftregIS
SIGNALiq:
STD_LOGIC_VECTOR(3downto0);
SIGNALs:
STD_LOGIC_VECTOR(1downto0);
BEGIN
sv=si&sO;
PROCESS(clk,r)
BEGIN
IF(r='"THEN
iqv="0000";
ELSIF(elk'eventANDelk―TT)HEN
CASEsIS
WHEN"00"=>null;
WHEN"01"=>iqv=dsr&din(3downto1);--rightWHEN"10"=>iqv=din(2downto0)&dsl;--leftWHEN"11"=>iqv=din;--loadWHENothers=>null;
ENDCASE;
ENDIF;
qoutv=iq;
ENDPROCESS;
ENDls74194;
19.用VHDL设计8421码十进制加法计数器解:
异步清零,同步置数
源代码:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_ARITH.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYeount10IS
PORT(elk,elr,load:
INSTD_LOGIC;
din:
INSTD_LOGIC_VECTOR(3downto0);
co:
OUTSTD_LOGIC;qout:
OUTSTD_LOGIC_VECTOR(3downto0));ENDcount10;
ARCHITECTUREcount10_archOFcount10IS
SIGNALiq:
STD_LOGIC_VECTOR(3downto0);BEGIN
PROCESS(clr,clk,load)
BEGIN
IF(clr='0THEN
iqv="0000";
ELSIF(elk'eventANDelk―TT)HEN
IF(load—)'THEN
iqv=din;
ELSIF(iq—9)THEN
iq<="0000";
ELSE
iq<—iq+1;
ENDIF;
ENDIF;
qout<—iq;
ENDPROCESS;
co<='WHENiq—"1001"ELSE
'0'
ENDeount10_areh;
20.用VHDL设计可逆格雷码计数器
解:
源代码:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYgray_eountIS
PORT(elk,y:
INSTD_LOGIC;qout:
OUTSTD_LOGIC_VECTOR(2downto0'';
ENDgray_eount;
ARCHITECTUREareh_grayOFgray_eountIS
SIGNALiq:
STD_LOGIC_VECTOR(2downto0';
BEGIN
PROCESS(elk'
BEGIN
IF(elk'eventANDelk—'1'T)HEN
IF(y—''1'THEN
CASEiqIS
WHEN"000"=>iq<="001";
WHEN"001"=>iqv="011";
WHEN"011"=>iqv="010";
WHEN"010"=>iqv="110";
WHEN"110"=>iq<="111";
WHEN"111"=>iq<="101";
WHEN"101"=>iq<="100";WHENothers=>iq<="000";
ENDCASE;ENDIF;
IF(y=')'THEN
CASEiqIS
WHEN"000"=>iq<="100";
WHEN"100"=>iq<="101";
WHEN"101"=>iq<="111";
WHEN"111"=>iq<="110";
WHEN"110"=>iq<="010";
WHEN"010"=>iq<="011";
WHEN"011"=>iq<="001";
WHENothers=>iq<="000";ENDCASE;
ENDIF;ENDIF;qout<=iq;
ENDPROCESS;
ENDarch_gray;
21.用VHDL设计有限状态机解:
源代码:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYasmIS
PORT(clk,k,reset:
INSTD_LOGIC;qout:
OUTSTD_LOGIC_VECTOR(1downto0));ENDasm;
ARCHITECTUREasm_archOFasmIS
TYPEasm_stIS(s0,s1,s2,s3;)
SIGNALcurrent_state,next_state:
asm_st;
BEGIN
reg:
PROCESS(clk,reset)
BEGIN
IF(rese='1'THEN
current_state<=s0;
ELSIF(elk'eventANDelk='TT)HENcurrent_state<=next_state
ENDIF;
ENDPROCESS;
com:
PROCESS(current_state,k)
BEGIN
CASEcurrent_stateISWHENs0=>qout<="00";
IF(k='O'T)HENnextstate<=s1;
ELSEnext_state<=s0;
ENDIF;
WHENs1=>qout<="01";
IF(k='0'T)HENnext_state<=s1;
ELSE
next_state<=s2;
ENDIF;
WHENs2=>qout<="10";
IF(k='0'T)HENnext_state<=s3;
ELSE
next_state<=s2;
ENDIF;
WHENs3=>qout<="11";
IF(k='0'T)HENnext_state<=s3;
ELSE
next_state<=s0;
ENDIF;
WHENothers=>next_state<=s0;
ENDCASE;
ENDPROCESS;
ENDasm_arch;
- 配套讲稿:
如PPT文件的首页显示word图标,表示该PPT已包含配套word讲稿。双击word图标可打开word文档。
- 特殊限制:
部分文档作品中含有的国旗、国徽等图片,仅作为作品整体效果示例展示,禁止商用。设计者仅对作品中独创性部分享有著作权。
- 关 键 词:
- 数字 逻辑 课后 第五