数字逻辑电路课程设计4bit模9加法器VHDL实现含完整.docx
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数字逻辑电路课程设计4bit模9加法器VHDL实现含完整.docx
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数字逻辑电路课程设计4bit模9加法器VHDL实现含完整
数字逻辑电路课程设计4bit模9加法器VHDL实现(含完整
UNIVERSITYOFELECTRONICSCIENCEANDTECHNOLOGYOFCHINA
数字逻辑设计
实验报告
实验题目:
4bit模9加法器
学生姓名:
指导老师:
一、实验内容
设计一个4bit模9加法器。
输入为两个4bit的二进制数,输出为两数相加后模9的结果。
其数学表达式为:
y=(x1+x2)mod9。
二、实验要求
1、功能性要求:
能够实现4bit无符号数的模9加法运算,即输入两个4比特数据时能够正确输出其相加并模9运算结果。
2、算法要求:
模加法器有多种算法,可采纳任意算法进行设计。
3、设计性要求:
采纳全加器、半加器和差不多门结构化描述。
能够编写TestBench文件,并利用Modelsim进行仿真。
在Modelsim仿真正确的基础上,能够生成bit文件并上板验证其正确性。
4、差不多上板要求:
在上板实验时,输入的两个4bit数采纳拨码开关输入,输出采纳LED灯进行显示。
三、设计思路
1、整体思路:
为了实现4bit无符号数的模9加法运算,能够先将两个4bit的加数a和b先分别模9,相加之后再模9得到最终结果。
2、模9器:
先找出读入的5bit数与模9后的4bit数之间的关系,画出卡诺图,再依照卡诺图得出其相应的逻辑表达式即可。
设读入的5bit数为carry、a、b、c、d,模9后得到的4bit数为w、x、y、z。
那么化简后得到的逻辑表达式分别为:
w=carry’ab’c’d’,
x=carry’bc+carry’a’b+carry’bd+carrya’b’c’d’,
y=carry’a’c+carry’cd+carry’abc’d’+carrya’b’c’d’,
z=carry’a’d+carry’acd’+carry’abd’+carrya’b’c’d’。
3、全加器:
全加器能够实现两个1bit数a、b和进位输入cin的相加,其真值表如下所示:
那个地点全加器由半加器和或门构成,其原理图如下:
4、半加器:
半加器是全加器的差不多组成单元,能够实现两个1bit数a和b的相加,并将进位输出,其真值表如下:
半加器由一个异或门和一个与门构成,其原理图如下所示:
5、数码管显示:
单个数码管一共有7个端〔不含小数点〕,用来表示组成一个数字的7个部分,故只要找到这7个段和模9后的4bit数间的对应关系,将其画出卡诺图并化简成逻辑表达式即可。
设得到的4bit数为a、b、c、d,那么得到的7段disa~disg的表达式为:
disa=b+d+c’a’+ac;
disb=c’+d+b’a’+ab;
disc=a+b’+c+d;
disd=ba’+c’a’+c’b+cb’a;
dise=d+ba’+c’a’;
disf=d+b’a’+ca’+cb’;
disg=d+ba’+c’b+ca’+cb’;
四、程序设计
1、顶层:
entitymainis
Port(a1:
inSTD_LOGIC;
a2:
inSTD_LOGIC;
a3:
inSTD_LOGIC;
a4:
inSTD_LOGIC;
b1:
inSTD_LOGIC;
b2:
inSTD_LOGIC;
b3:
inSTD_LOGIC;
b4:
inSTD_LOGIC;
ans1:
outSTD_LOGIC;
ans2:
outSTD_LOGIC;
ans3:
outSTD_LOGIC;
ans4:
outSTD_LOGIC;
disA:
outSTD_LOGIC;
disB:
outSTD_LOGIC;
disC:
outSTD_LOGIC;
disD:
outSTD_LOGIC;
disE:
outSTD_LOGIC;
disF:
outSTD_LOGIC;
disG:
outSTD_LOGIC
);
endmain;
architectureBehavioralofmainis
COMPONENTfulladder
PORT(
a:
INstd_logic;
b:
INstd_logic;
ci:
INstd_logic;
s:
OUTstd_logic;
co:
OUTstd_logic
);
ENDCOMPONENT;
COMPONENTmod9
PORT(
carry:
INstd_logic;
a:
INstd_logic;
b:
INstd_logic;
c:
INstd_logic;
d:
INstd_logic;
w:
OUTstd_logic;
x:
OUTstd_logic;
y:
OUTstd_logic;
z:
OUTstd_logic
);
ENDCOMPONENT;
COMPONENTdis
PORT(
a:
INstd_logic;
b:
INstd_logic;
c:
INstd_logic;
d:
INstd_logic;
disa:
OUTstd_logic;
disb:
OUTstd_logic;
disc:
OUTstd_logic;
disd:
OUTstd_logic;
dise:
OUTstd_logic;
disf:
OUTstd_logic;
disg:
OUTstd_logic
);
ENDCOMPONENT;
signalc1,c2,c3,c4,s1,s2,s3,s4,ans11,ans22,ans33,ans44,a11,a22,a33,a44,b11,b22,b33,b44,temp:
std_logic;
begin
--mod9_a--
temp<='0';
Inst_mod9_a:
mod9PORTMAP(
carry=>temp,--carry是最高位
a=>a4,
b=>a3,
c=>a2,
d=>a1,--d是最低位
w=>a44,--w是最高位
x=>a33,
y=>a22,
z=>a11--z是最低位
);
--mod9_b--
Inst_mod9_b:
mod9PORTMAP(
carry=>temp,--carry是最高位
a=>b4,
b=>b3,
c=>b2,
d=>b1,--d是最低位
w=>b44,--w是最高位
x=>b33,
y=>b22,
z=>b11--z是最低位
);
--add--
Inst_fulladder_add1:
fulladderPORTMAP(
a=>a11,
b=>b11,
ci=>temp,
s=>s1,
co=>c1
);
Inst_fulladder_add2:
fulladderPORTMAP(
a=>a22,
b=>b22,
ci=>c1,
s=>s2,
co=>c2
);
Inst_fulladder_add3:
fulladderPORTMAP(
a=>a33,
b=>b33,
ci=>c2,
s=>s3,
co=>c3
);
Inst_fulladder_add4:
fulladderPORTMAP(
a=>a44,
b=>b44,
ci=>c3,
s=>s4,
co=>c4
);
--mod9_ans--
Inst_mod9_ans:
mod9PORTMAP(
carry=>c4,--carry是最高位,对应最后一个进位c4
a=>s4,
b=>s3,
c=>s2,
d=>s1,--d是最低位,对应s1
w=>ans44,--w是最高位,对应ans4
x=>ans33,
y=>ans22,
z=>ans11--z是最低位,对应ans1
);
--not--
ans1<=notans11;
ans2<=notans22;
ans3<=notans33;
ans4<=notans44;
--dis--
Inst_dis:
disPORTMAP(
a=>ans11,--最低位(读入取反之前的ans)
b=>ans22,
c=>ans33,
d=>ans44,--最高位
disa=>disA,
disb=>disB,
disc=>disC,
disd=>disD,
dise=>disE,
disf=>disF,
disg=>disG
);
endBehavioral;
2、模9器:
entitymod9is
Port(carry:
inSTD_LOGIC;
a:
inSTD_LOGIC;
b:
inSTD_LOGIC;
c:
inSTD_LOGIC;
d:
inSTD_LOGIC;
w:
outSTD_LOGIC;
x:
outSTD_LOGIC;
y:
outSTD_LOGIC;
z:
outSTD_LOGIC);
endmod9;
architectureBehavioralofmod9is
signalnota,notb,notc,notd,notcarry:
std_logic;
Begin
--not--
nota<=nota;
notb<=notb;
notc<=notc;
notd<=notd;
notcarry<=notcarry;
--mod9--
w<=aandnotbandnotcandnotdandnotcarry;
x<=(bandc)or(bandnota)or(bandd);
y<=(notaandc)or(candd)or(aandbandnotcandnotd);
z<=(notaandd)or(aandcandnotd)or(aandbandnotd);
endBehavioral;
3、全加器:
entityfulladderis
Port(a:
inSTD_LOGIC;
b:
inSTD_LOGIC;
ci:
inSTD_LOGIC;
s:
outSTD_LOGIC;
co:
outSTD_LOGIC);
endfulladder;
architectureBehavioraloffulladderis
COMPONENThalfadder
PORT(
a:
INstd_logic;
b:
INstd_logic;
s:
OUTstd_logic;
c:
OUTstd_logic
);
ENDCOMPONENT;
COMPONENTor2i
PORT(
i1:
INstd_logic;
i2:
INstd_logic;
o:
OUTstd_logic
);
ENDCOMPONENT;
signals1,c1,c2:
std_logic;
begin
Inst_halfadder_sum1:
halfadderPORTMAP(
a=>a,
b=>b,
s=>s1,
c=>c1
);
Inst_halfadder_sum2:
halfadderPORTMAP(
a=>ci,
b=>s1,
s=>s,
c=>c2
);
Inst_or2i_co:
or2iPORTMAP(
i1=>c1,
i2=>c2,
o=>co
);
endBehavioral;
4、半加器:
entityhalfadderis
Port(a:
inSTD_LOGIC;
b:
inSTD_LOGIC;
s:
outSTD_LOGIC;
c:
outSTD_LOGIC);
endhalfadder;
architectureBehavioralofhalfadderis
COMPONENTnoti
PORT(
i:
INstd_logic;
o:
OUTstd_logic
);
ENDCOMPONENT;
COMPONENTand2i
PORT(
i1:
INstd_logic;
i2:
INstd_logic;
o:
OUTstd_logic
);
ENDCOMPONENT;
COMPONENTor2i
PORT(
i1:
INstd_logic;
i2:
INstd_logic;
o:
OUTstd_logic
);
ENDCOMPONENT;
signalnota,notb,s1,s2:
std_logic;
begin
--not--
Inst_noti_nota:
notiPORTMAP(
i=>a,
o=>nota
);
Inst_noti_notb:
notiPORTMAP(
i=>b,
o=>notb
);
--s--
Inst_and2i_s1:
and2iPORTMAP(
i1=>nota,
i2=>b,
o=>s1
);
Inst_and2i_s2:
and2iPORTMAP(
i1=>a,
i2=>notb,
o=>s2
);
Inst_or2i_s:
or2iPORTMAP(
i1=>s1,
i2=>s2,
o=>s
);
--c--
Inst_and2i_c:
and2iPORTMAP(
i1=>a,
i2=>b,
o=>c
);
endBehavioral;
5、数码管显示:
entitydisis
Port(a:
inSTD_LOGIC;
b:
inSTD_LOGIC;
c:
inSTD_LOGIC;
d:
inSTD_LOGIC;
disa:
outSTD_LOGIC;
disb:
outSTD_LOGIC;
disc:
outSTD_LOGIC;
disd:
outSTD_LOGIC;
dise:
outSTD_LOGIC;
disf:
outSTD_LOGIC;
disg:
outSTD_LOGIC);
enddis;
architectureBehavioralofdisis
signalnota,notb,notc,notd,disaa,disbb,discc,disdd,disee,disff,disgg:
std_logic;
begin
--not--
nota<=nota;
notb<=notb;
notc<=notc;
notd<=notd;
--dis--
disaa<=bordor(notcandnota)or(canda);
disbb<=notcordor(notbandnota)or(banda);
discc<=aornotborcord;
disdd<=(bandnota)or(notcandnota)or(notcandb)or(candnotbanda);
disee<=dor(bandnota)or(notcandnota);
disff<=dor(notbandnota)or(candnota)or(candnotb);
disgg<=dor(bandnota)or(notcandb)or(candnota)or(candnotb);
--not--
disa<=notdisaa;
disb<=notdisbb;
disc<=notdiscc;
disd<=notdisdd;
dise<=notdisee;
disf<=notdisff;
disg<=notdisgg;
endBehavioral;
五、仿真与硬件调试
1、仿真:
〔1〕顶层仿真
1.仿真文件:
LIBRARYieee;
USEieee.std_logic_1164.ALL;
ENTITYtest2IS
ENDtest2;
ARCHITECTUREbehaviorOFtest2IS
--ComponentDeclarationfortheUnitUnderTest(UUT)
COMPONENTmain
PORT(
a1:
INstd_logic;
a2:
INstd_logic;
a3:
INstd_logic;
a4:
INstd_logic;
b1:
INstd_logic;
b2:
INstd_logic;
b3:
INstd_logic;
b4:
INstd_logic;
ans1:
OUTstd_logic;
ans2:
OUTstd_logic;
ans3:
OUTstd_logic;
ans4:
OUTstd_logic;
disA:
OUTstd_logic;
disB:
OUTstd_logic;
disC:
OUTstd_logic;
disD:
OUTstd_logic;
disE:
OUTstd_logic;
disF:
OUTstd_logic;
disG:
OUTstd_logic
);
ENDCOMPONENT;
--Inputs
signala1:
std_logic:
='0';
signala2:
std_logic:
='0';
signala3:
std_logic:
='0';
signala4:
std_logic:
='0';
signalb1:
std_logic:
='0';
signalb2:
std_logic:
='0';
signalb3:
std_logic:
='0';
signalb4:
std_logic:
='0';
--Outputs
signalans1:
std_logic;
signalans2:
std_logic;
signalans3:
std_logic;
signalans4:
std_logic;
signaldisA:
std_logic;
signaldisB:
std_logic;
signaldisC:
std_logic;
signaldisD:
std_logic;
signaldisE:
std_logic;
signaldisF:
std_logic;
signaldisG:
std_logic;
--Noclocksdetectedinportlist.Replace
--appropriateportname
BEGIN
--InstantiatetheUnitUnderTest(UUT)
uut:
mainPORTMAP(
a1=>a1,
a2=>a2,
a3=>a3,
a4=>a4,
b1=>b1,
b2=>b2,
b3=>b3,
b4=>b4,
ans1=>ans1,
ans2=>ans2,
ans3=>ans3,
ans4=>ans4,
disA=>disA,
disB=>disB,
disC=>disC,
disD=>disD,
disE=>disE,
disF=>disF,
disG=>disG
);
--Stimulusprocess
stim_proc:
process
begin
a4<='0';a3<='0';a2<='0';a1<='0';
b4<='0';b3<='0';b2<='0';b1<='0';
waitfor100ns;
a4<='0';a3<='0';a2<='0';a1<='0';
b4<='0';b3<='0';b2<='0';b1<='1';
waitfor100ns;
a4<='0';a3<='0';a2<='0';a1<='0';
b4<='0';b3<='0';b2<='1';b1<='0';
waitfor100ns;
a4<='0';a3<='0';a2<='0';a1<='0';
b4<='0';b3<='0';b2<='1';b1<='1';
waitfor100ns;
a4<='0';a3<='0';a2<='0';a1<='0';
b4<='0';b3<='1';b2<='0';b1<='0';
waitfor100ns;
a4
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