JESD79-3F.pdf
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JESD79-3F.pdf
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JEDECSOLIDSTATETECHNOLOGYASSOCIATIONJESD79-3FJULY2012JEDECSTANDARDDDR3SDRAMStandard(RevisionofJESD79-3E,July2010)NOTICEJEDECstandardsandpublicationscontainmaterialthathasbeenprepared,reviewed,andapprovedthroughtheJEDECBoardofDirectorslevelandsubsequentlyreviewedandapprovedbytheJEDEClegalcounsel.JEDECstandardsandpublicationsaredesignedtoservethepublicinterestthrougheliminatingmisunderstandingsbetweenmanufacturersandpurchasers,facilitatinginterchangeabilityandimprovementofproducts,andassistingthepurchaserinselectingandobtainingwithminimumdelaytheproperproductforusebythoseotherthanJEDECmembers,whetherthestandardistobeusedeitherdomesticallyorinternationally.JEDECstandardsandpublicationsareadoptedwithoutregardtowhetherornottheiradoptionmayinvolvepatentsorarticles,materials,orprocesses.BysuchactionJEDECdoesnotassumeanyliabilitytoanypatentowner,nordoesitassumeanyobligationwhatevertopartiesadoptingtheJEDECstandardsorpublications.TheinformationincludedinJEDECstandardsandpublicationsrepresentsasoundapproachtoproductspecificationandapplication,principallyfromthesolidstatedevicemanufacturerviewpoint.WithintheJEDECorganizationthereareprocedureswherebyaJEDECstandardorpublicationmaybefurtherprocessedandultimatelybecomeanANSIstandard.Noclaimstobeinconformancewiththisstandardmaybemadeunlessallrequirementsstatedinthestandardaremet.Inquiries,comments,andsuggestionsrelativetothecontentofthisJEDECstandardorpublicationshouldbeaddressedtoJEDECattheaddressbelow,orcall(703)907-7559orwww.jedec.orgPublishedbyJEDECSolidStateTechnologyAssociation20123103North10thStreet,Suite240SouthArlington,VA22201Thisdocumentmaybedownloadedfreeofcharge;howeverJEDECretainsthecopyrightonthismaterial.Bydownloadingthisfiletheindividualagreesnottochargefororreselltheresultingmaterial.PRICE:
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JEDECSolidStateTechnologyAssociation3103North10thStreet,Suite240SouthArlington,Virginia22201orcall(703)907-7559Thispageleftblank.JEDECStandardNo.79-3FContentsi1Scope.12DDR3SDRAMPackagePinoutandAddressing.32.1DDR3SDRAMx4BalloutusingMO-207.32.11.1512Mb.152.11.21Gb.152.11.32Gb.152.11.44Gb.152.11.58Gb.163FunctionalDescription.173.1SimplifiedStateDiagram.173.3.1Power-upInitializationSequence.193.3.2ResetInitializationwithStablePower.213.4.1ProgrammingtheModeRegisters.223.4.2ModeRegisterMR0.233.4.3ModeRegisterMR1.273.4.4ModeRegisterMR2.303.4.5ModeRegisterMR3.324DDR3SDRAMCommandDescriptionandOperation.334.1CommandTruthTable.334.3NoOPeration(NOP)Command.364.4DeselectCommand.364.6.1DLL“on”toDLL“off”Procedure.384.6.2DLL“off”toDLL“on”Procedure.394.8.1DRAMsettingforwriteleveling&DRAMterminationfunctioninthatmode.434.8.2ProcedureDescription.434.8.3WriteLevelingModeExit.454.9.1Self-RefreshTemperatureRange-SRT.464.10.1MPRFunctionalDescription.494.10.2MPRRegisterAddressDefinition.504.10.3RelevantTimingParameters.504.10.4ProtocolExample.504.12PRECHARGECommand.554.13.1READBurstOperation.564.13.3BurstReadOperationfollowedbyaPrecharge.664.14.1DDR3BurstOperation.684.14.2WRITETimingViolations.684.14.3WriteDataMask.694.14.4tWPRECalculation.704.14.5tWPSTCalculation.704.17.1Power-DownEntryandExit.814.17.2Power-Downclarifications-Case1.864.17.3Power-Downclarifications-Case2.875On-DieTermination(ODT).895.1ODTModeRegisterandODTTruthTable.89JEDECStandardNo.79-3FContentsii5.2SynchronousODTMode.905.2.1ODTLatencyandPostedODT.905.2.2TimingParameters.905.2.3ODTduringReads.925.3.1FunctionalDescription:
.945.3.2ODTTimingDiagrams.955.4.1SynchronoustoAsynchronousODTModeTransitions.1015.4.2SynchronoustoAsynchronousODTModeTransitionduringPower-DownEntry.1015.4.3AsynchronoustoSynchronousODTModeTransitionduringPower-DownExit.1045.4.4AsynchronoustoSynchronousODTModeduringshortCKEhighandshortCKElowperiods.1055.5.1ZQCalibrationDescription.1075.5.2ZQCalibrationTiming.1085.5.3ZQExternalResistorValue,Tolerance,andCapacitiveloading.1086AbsoluteMaximumRatings.1096.1AbsoluteMaximumDCRatings.1096.2DRAMComponentOperatingTemperatureRange.1097AC&DCOperatingConditions.1117.1RecommendedDCOperatingConditions.1118ACandDCInputMeasurementLevels.1138.1ACandDCLogicInputLevelsforSingle-EndedSignals.1138.1.1ACandDCInputLevelsforSingle-EndedCommandandAddressSignals.1138.3ACandDCLogicInputLevelsforDifferentialSignals.1168.3.1Differentialsignaldefinition.1168.3.2Differentialswingrequirementsforclock(CK-CK#)andstrobe(DQS-DQS#).1168.3.3Single-endedrequirementsfordifferentialsignals.1178.4DifferentialInputCrossPointVoltage.1188.6SlewRateDefinitionsforDifferentialInputSignals.1209ACandDCOutputMeasurementLevels.1219.1SingleEndedACandDCOutputLevels.1219.2DifferentialACandDCOutputLevels.1219.6.1AddressandControlOvershootandUndershootSpecifications.1259.6.2Clock,Data,StrobeandMaskOvershootandUndershootSpecifications.1269.7.1OutputDriverTemperatureandVoltagesensitivity.1289.8.1On-DieTermination(ODT)LevelsandI-VCharacteristics.1309.8.2ODTDCElectricalCharacteristics.1319.8.3ODTTemperatureandVoltagesensitivity.1349.9ODTTimingDefinitions.1349.9.1TestLoadforODTTimings.1349.9.2ODTTimingDefinitions.13510IDDandIDDQSpecificationParametersandTestConditions.139JEDECStandardNo.79-3FContentsiii10.1IDDandIDDQMeasurementConditions.13911Input/OutputCapacitance.15311.1Input/OutputCapacitance.15312.15512.1ClockSpecification.15512.1.1DefinitionfortCK(avg).15512.1.2DefinitionfortCK(abs).15512.1.3DefinitionfortCH(avg)andtCL(avg).15512.1.4DefinitionfortJIT(per)andtJIT(per,lck).15612.1.5DefinitionfortJIT(cc)andtJIT(cc,lck).15612.1.6DefinitionfortERR(nper).15612.2Refreshparametersbydevicedensity.15613ElectricalCharacteristicsandACTiming.16713.1TimingParametersforDDR3-800,DDR3-1067,DDR3-1333,andDDR3-1600.16713.6.1DataSetup,HoldandSlewRateDeratingofDDR3-1866/2133.190JEDECStandardNo.79-3FListofFiguresivFigure1Qual-stacked/Quad-dieDDR3SDRAMx4rankassociation.12Figure2Qual-stacked/Quad-dieDDR3SDRAMx8rankassociation.12Figure3Qual-stacked/Quad-dieDDR3SDRAMx16rankassociation.12Figure4SimplifiedStateDiagram.17Figure5ResetandInitializationSequenceatPower-onRamping.20Figure6ResetProcedureatPowerStableCondition.21Figure7tMRDTiming.22Figure8tMODTiming.22Figure9MR0Definition.24Figure10MR1Definition.27Figure11MR2Definition.30Figure12MR3Definition.32Figure13DLL-offmodeREADTimingOperation.37Figure14DLLSwitchSequencefromDLL-ontoDLL-off.38Figure15DLLSwitchSequencefromDLLOfftoDLLOn.39Figure16ChangeFrequencyduringPrechargePower-down.41Figure17WriteLevelingConcept.42Figure18TimingdetailsofWritelevelingsequenceDQS-DQS#iscapturingCK-CK#lowatT1andCK-CK#highatT2.44Figure19TimingdetailsofWritelevelingexit.45Figure20MPRBlockDiagram.48Figure21MPRReadoutofpredefinedpattern,BL8fixedburstorder,singlereadout.51Figure22MPRReadoutofpredefinedpattern,BL8fixedburstorder,back-to-backreadout.52Figure23MPRReadoutpredefinedpattern,BC4,lowernibblethenuppernibble.53Figure24MPRReadoutofpredefinedpattern,BC4,uppernibblethenlowernibble.54Figure25READBurstOperationRL=5(AL=0,CL=5,BL8).56Figure26READBurstOperationRL=9(AL=4,CL=5,BL8).56Figure27READTimingDefinition.57Figure28ClocktoDataStrobeRelationship.58Figure29DataStrobetoDataRelationship.59Figure30tLZandtHZmethodforcalculatingtransitionsandendpoints.60Figure31MethodforcalculatingtRPREtransitionsandendpoints.61Figure32MethodforcalculatingtRPSTtransitionsandendpoints.61Figure33READ(BL8)toREAD(BL8).62Figure34NonconsecutiveREAD(BL8)toREAD(BL8),tCCD=5.62Figure35READ(BC4)toREAD(BC4).63Figure36READ(BL8)toWRITE(BL8).63Figure37READ(BC4)toWRITE(BC4)OTF.64Figure38READ(BL8)toREAD(BC4)OTF.64Figure39READ(BC4)toREAD(BL8)OTF.65Figure40READ(BC4)toWRITE(BL8)OTF.65Figure41READ(BL8)toWRITE(BC4)OTF.66Figure42READtoPRECHARGE,RL=5,AL=0,CL=5,tRTP=4,tRP=5.67Figure43READtoPRECHARGE,RL=8,AL=CL-2,CL=5,tRTP=6,tRP=5.67Figure44WriteTimingDefinitionandParameters.69Figure45MethodforcalculatingtWPREtransitionsandendpoints.70JEDECStandardNo.79-3FListofFiguresvFigure46MethodforcalculatingtWPSTtransitionsandendpoints.70Figure47WRITEBurstOperationWL=5(AL=0,CWL=5,BL8).71Figure48WRITEBurstOperationWL=9(AL=CL-1,CWL=5,BL8).71Figure49WRITE(BC4)toREAD(BC4)Operation.72Figure50WRITE(BC4)toPRECHARGEOperation.72Figure51WRITE(BC4)OTFtoPRECHARGEOperation.72Figure52WRITE(BL8)toWRITE(BL8).73Figure53WRITE(BC4)toWRITE(BC4)OTF.73Figure54WRITE(BL8)toREAD(BC4/BL8)OTF.74Figure55WRITE(BC4)toREAD(BC4/BL8)OTF.74Figure56WRITE(BC4)toREAD(BC4).75Figure57WRITE(BL8)toWRITE(BC4)OTF.75Figure58WRITE(BC4)toWRITE(BL8)OTF.76Figure59RefreshCommandTiming.77Figure60PostponingRefreshCommands(Example).77Figure61Pulling-inRefreshCommands(Example).78Figure62Self-RefreshEntry/ExitTiming.80Figure63ActivePower-DownEntryandExitTimingDiagram.82Figure64Power-DownEntryafterReadandReadwith
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